Due to the complexity and nonlinearity of analog circuit design, design automation is still a challenging field. With the current progress in AI and its success in other areas, new possibilities arise for analog design. In this seminar the state of the art in AI for analog synthesis should be analyzed and a structured overview of different methods be developed.

Research paper to start with:

·      G. Wolfe and R. Vemuri, "Extraction and use of neural network models in automated synthesis of operational amplifiers," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 2, pp. 198-212, Feb. 2003, doi: 10.1109/TCAD.2002.806600.

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1174095&isnumber=26375

One of the most common approaches in optimization is to make use of first and second derivatives, in order to find a minimum of a target function. In many cases though, this is not a viable option, as derivatives might not be available, or the function might not be differentiable at all.
For such problems, we need algorithms, that work without derivatives. This can be achieved for example using finite differences or interpolation.
One important algorithm family are the algorithms NEWUOA and BOBYQA by M. J. D. Powell.
The goal of this seminar is to gather works, that evaluate the performance of those algorithms. Furthermore, we want to create a performance matrix that puts Powell’s algorithms into relation with traditional algorithms over a range of different optimization problems.

Paper for BOBYQA (Has not to be read enirely!):
www.damtp.cam.ac.uk/user/na/NA_papers/NA2009_06.pdf

Knowledge in optimization and basic linear algebra is recommended.

Exploring the scheduling methods used when deploying multiple
inference graphs/tasks onto a single, ideally heterogeneous, platform

Looking into currently used heuristic methods for finding
mappings from network inference tasks to hardware

Modern design approaches for embedded systems rely heavily on abstract models of the targeted hardware, to allow early and fast simulations of the system. Typical examples of such models are Virtual Prototypes (VPs) and Instruction Set Simulators (ISSs).

While VPs and ISSs offer high simulation speeds, they are not capable of providing reliable information regarding the systems performance (i.e. its timing behavior). Cycle Accurate Simulators (CAS) are capable of providing more accurate data on the systems performance, but at the cost of reduced simulation speeds.

GVSoC is a highly flexible full-platform simulator that offers high simulation speeds compared to other CASs, and has a typical error rate of below 10%.

Modern design approaches for embedded systems rely heavily on abstract models of the targeted hardware, to allow early and fast simulations of the system. Typical examples of such models are Virtual Prototypes (VPs) and Instruction Set Simulators (ISSs).

While VPs and ISSs offer high simulation speeds, they are not capable of providing reliable information regarding the systems performance (i.e. its timing behavior). Cycle Accurate Simulators (CAS) are capable of providing more accurate data on the systems performance, but at the cost of reduced simulation speeds.

The ComCAS simulator explores the use of "compiled simulation" to increase the simulation speed of a CAS.

Electronic Design Automation (EDA) has enabled rapid speedup in the development of new electronic systems and devices. By means of hierarchical design paradigms, logic synthesis or floorplanning algorithms and timing analysis, etc. the time to market for new designs can be reduced, while the system complexity increases. However, most intellectual property in this domain is protected by major vendors. But recently, the attention on open-source projects in EDA has grown. For example, with OpenRoad [1], a RTL-to-GDSII design flow is under developement to make ASIC digital design process more accessible.

The goal of this topic should be a survey on current work in open-source tools for EDA. Major projects should be identified and its benefits and limitations should be investigated.

[1] KAHNG, Andrew B.; SPYROU, Tom. The OpenROAD project: Unleashing hardware innovation. In: Proc. GOMAC. 2021.

Abstract— Antenna problem is a phenomenon of plasma induced gate oxide degradation. It directly affects manufacturability of VLSI circuits, especially in deep-submicron technology using high density plasma. Diode insertion is a very effective way to solve this problem Ideally diodes are inserted directly under the wires that violate antenna rules. But in today's high-density VLSI layouts, there is simply not enough room for "under-the-wire" diode insertion for all wires. Thus it is necessary to insert many diodes at legal "off-wire" locations and extend the antenna-rule violating wires to connect to their respective diodes. Previously only simple heuristic algorithms were available for this diode insertion and routing problem. In this paper we show that the diode insertion and routing problem for an arbitrary given number of routing layers can be optimally solved in polynomial time. Our algorithm guarantees to find a feasible diode insertion and routing solution whenever one exists. Moreover we can guarantee to find a feasible solution to minimize a cost function of the form /spl alpha/ /spl middot/ L + /spl beta/ /spl middot/ N where L is the total length of extension wires and N is the total number of Was on the extension wires. Experimental results show that our algorithm is very efficient.

Abstract— This paper presents a general multi-layer area router based on a novel grid construction scheme. The grid construction scheme produces more wiring tracks than the normal uniform grid scheme and accounts for differing design rules of the layers involved. Initial routing performed on the varying capacity grid is followed by a layer assignment stage. Routing completion is ensured by iterating local and global modifications in the layer assignment stage. Our router has been incorporated into the Custom Cell Synthesis project at MCC and has shown improved results for cell synthesis problems when compared with the router Mighty which was used in earlier versions of the project.