Chair of Electronic Design Automation, Technical University of Munich, Arcisstr. 21, 80333 Munich, Germany
Friday, April 21, 2023, 9am – 3pm, Hall 1180 (https://portal.mytum.de/campus/roomfinder/roomfinder_viewmap?mapid=12&roomid=1180@0501)
9am Analog/Mixed Signal/Heterogeneous Design - Hierarchy of Needs for the Designer and Need of Hierarchy for CAD Tools, Günhan Dündar, Boğaziçi University, Istanbul, Turkey
10am The Use of Hierarchical Sub-circuit Recognition in a Fully Automatic Analog Schematic to Layout Solution, Matthew Buckley, Pulsic Ltd, Newcastle Upon Tyne, UK
11am Identifying and Using Hierarchy in Analog Layout Synthesis, Sachin S. Sapatnekar, University of Minnesota, Minneapolis (MN), US
1pm PD-Gen: A novel Object-Oriented Procedural Physical Design (OO-PPD) tool for Analog P&R, Husni Habal, Infineon Technologies AG, Munich, Germany
2pm Learning from the Implicit Hierarchy in an Analog Netlist, Helmut Graeb, Chair of Electronic Design Automation, Technical University of Munich
3pm End of workshop
Registration under https://wiki.tum.de/x/_YOUVQ Please register till Friday, April 14.
Abstracts and Bios
Analog/Mixed Signal/Heterogeneous Design - Hierarchy of Needs for the Designer and Need of Hierarchy for CAD Tools
Günhan Dündar, Boğaziçi University, Istanbul, Turkey
In the past 20 years, many “design automation” systems have been proposed for analog design, mostly by the academia. However, very few have enjoyed widespread acceptance, let alone commercial success. The talk will initially concentrate on the analog designer’s point of view, both from the academia, and from the industry regarding the usage of automation tools. The possible utilization of CAD tools in the design process will be evaluated, whilst critically investigating obstacles that hinder streamlining these tools into the design process. The focus of this talk will be on modeling of analog blocks with particular emphasis in hierarchical design, whereby bottom-up design using CAD tools, and sharing of information between different levels will be explored. Also, robust design immune to variability, aging, and radiation will be briefly mentioned. Finally, the usability of analog IP will be discussed along with some possible specifications and definitions.
Günhan Dündar was born in İstanbul, Turkey in 1969. He obtained his BS and MS from Boğaziçi University, İstanbul, Turkey, in 1989 and 1991, and his PhD from Rensselaer Polytechnic Institute, USA in 1993, all in electrical engineering. Since 1994, he has been with Boğaziçi University, where he is currently a professor. He has also been with EPFL and TU München as an invited professor. At Boğaziçi University, he leads the BETA: Boğaziçi University Electronics Design Research Laboratory, focusing on academic research and industry consultation in electronics design aligned with his research interests in the design of analog integrated circuits and design methodologies. In 2017, he co-founded the MedTech company GlakoLens. He has several hundred publications in international journals and conferences as well as patents, books, and book chapters.
The Use of Hierarchical Sub-circuit Recognition in a Fully Automatic Analog Schematic to Layout Solution
Matthew Buckley, Pulsic Ltd, Newcastle Upon Tyne, UK
Pulsic’s Animate is a fully automatic schematic to layout solution. It considers multiple layout topologies to create high-quality layouts from the schematic in minutes and reduces costly design flow iterations. As well as obeying existing design hierarchy Animate automatically recognizes common analog circuit topologies and uses these as well as other circuit partitioning methods to drive the placement quality. In this talk we will present the Animate technology and discuss its use of hierarchy.
Matthew Buckley is a Chief Software Engineer in EDA software development. He has 10 years of experience in this field and currently leads the Animate Premium Product team at Pulsic. Matthew holds a PhD. in Applied Mathematics and Master’s Degree in Mathematics from Newcastle University.
Identifying and Using Hierarchy in Analog Layout Synthesis
Sachin S. Sapatnekar, University of Minnesota, Minneapolis (MN), USA
The use of hierarchy is critical in decomposing the analog synthesis problem into bite-sized chunks that can be optimally handled by an optimizer. This talk describes our experiences with hierarchy while developing the ALIGN layout synthesis engine: in particular, describing techniques for identifying hierarchies as well as layout-level optimizations for hierarchical blocks.
Sachin Sapatnekar teaches at the University of Minnesota. His research is related to developing CAD techniques for the analysis and optimization of circuit performance, and with particular focus over the last 5 years on analog design automation. He is a Fellow of the IEEE and the ACM.
PD-Gen: A novel Object-Oriented Procedural Physical Design (OO-PPD) tool for Analog P&R
Husni Habal, Infineon Technologies AG, Munich, Germany
PD-Gen is a novel tool for semi-automatic and procedural analog circuit placement and routing (P&R) developed at Infineon Technologies. It is technology-agnostic and scalable to meet the needs of many projects and customers.
PD-Gen is an object-oriented design tool because it is built from the bottom up using layout modules and constraint groups. These objects encapsulate the procedures needed to generate a layout and are configured through a set of design parameters. Module are glued together using constraint groups to construct larger blocks in a recursive manner – from a basic transistor array to an OTA and up to a complete IP.
The main objective of PD-Gen development is to encourage design and IP reuse and reduce the time-to-tapeout . The tool output is a parameterized layout generator that can be used to create many instances of an original circuit topology, but resized to meet new electrical specifications or remapped to a new technology node.
In this presentation, the basic principles of PD-Gen will be presented, then used to construct an example circuit layout.
Husni Habal received a doctorate degree in electrical engineering from the Technical University of Munich (TUM) in 2013. Funded by the German Research Foundation, he held a post-doctorate position at the institute for Electronic Design Automation, TUM, until 2016 with a focus on the modeling of transistor aging mechanisms for numerical simulation and analog circuit optimization).
In 2016, he joined Infineon Technologies AG where he worked on the development of in-house front- and back-end analog design tools. He is currently the technical lead of the Analog Design Automation (ADA) product group. His team initiates many in-house methodology improvement projects and participates in German and European funding projects alongside leading universities and research institutes. Recent funding projects include GenerIC, PLASMA, and HoloDEC.
Learning from the Implicit Hierarchy in an Analog Netlist
Helmut Graeb, Chair of Electronic Design Automation, Technical University of Munich
Analog circuit design is characterized by a plethora of implicit design and technology aspects available to the experienced designer. In order to create useful computer-aided design methods, this implicit knowledge has to be captured in a systematic and hierarchical
way. A key approach to this goal is to "learn" the knowledge from the netlist of an analog circuit. This requires a library of structural and functional blocks for analog circuits together with their individual constraints and performance equations, graph techniques to recognize blocks that can have different structural implementations and I/O pins, as well as synthesis methods that exploit the learned knowledge. In this contribution, we will present
how to make use of the functional and structural hierarchy of operational amplifiers in sizing, synthesis and layout.
Helmut Graeb received the Master/PhD/habilitation degrees in Electrical Engineering from TUM in 1986, 1993, 2008. Since 1987, he is working at TUM on analog design automation. He is an IEEE Fellow and co-founder of MunEDA GmbH.