Current Projects

Physical Design for Microfluidic Large-Scale Integration with Partitioning and Floorplanning

DFG Research Grant (since 2023)

  • Exploration of mLSI design partitioning and floorplanning to solve the physical design problem in a hierarchical manner.

Bandwidth Maximization and Allocation for Wavelength-Routed Optical Networks-on-Chip (WRONoC)

DFG Research Grant (since 2023)

  • WRONoC topology synthesis considering bandwidth maximization and allocation.

Design and Integration of Test Module for Microfluidic Large-Scale Integration (mLSI)

DFG Research Grant (since 2021)

  • Design and integration of microfluidic test modules, as well as the synthesis of testable designs.

Combining Topology Synthesis and Physical Design for Wavelength-Routed Optical Networks-on-Chip (WRONoC) — Design Automation Using Physical Layout Templates

DFG Research Grant (since 2020)

  • Development of comprehensive template-based design automation methods for wavelength-routed optical network-on-chip

Completed Projects

Automatic Analysis of PCB Schematic Designs

Collaborative project with Huawei (16.11.2021-15.05.2022)

Netlist-driven Design of MEMS for Applications in Optics and Robotics (MEMS2015)

BMBF Collaborative Project (1.7.2012-30.06.2015)

  • Structural analysis and sizing of MEMS
Methods for automatic optimization of analogue integrated circuits with regard to ageing

DFG Research Grant (01.02.2012-31.01.2015)

Design and Architectures of Dependable Embedded Systems (SPP1500)

DFG Priority Programme 1500 (01.2011-12.2015)

  • Lifting Device-Level Characteristics for Error Resilient System Level Design: A Crosslayer Approach
Secure Systems by Seamless Verification (SANITAS)

BMBF Collaborative Project (01.10.2009-30.09.2012)

  • Optimized Modeling of non-functional properties for TLM/TLM+ models (with Infineon Technologies)
Design of Robust Nano-Electronic Systems (ROBUST)

BMBF Cluster Project (01.04.2009-31.03.2012)

  • Analysis methods for digital modules (with Infineon Technologies)
  • Robustness optimization on gate level (with Infineon Technologies)
Highly Optimized Design Methods for Yield and Reliability (HONEY)

BMBF Collaborative Project (01.12.2007-30.11.2010)

  • Tolerance Pareto Optimization (with MunEDA)
  • Reliability analysis on gate level (with Infineon Technologies)
Technology based Modeling and Analysis at the 65-nm Node Considering Statistical Spreads (SIGMA65)

BMBF Collaborative Project (01.10.2006-31.12.2009)

  • Statistical Static Timing Analysis (with Infineon Technologies)
Analog/Mixed-Signal Design for Test

Infineon Technologies (01.11.2006-31.10.2009)

Verification of Analog Circuits (VERONA)

BMBF Collaborative Project (01.06.2006-31.05.2009)

  • Pareto Optimization (with MunEDA)
Structural Analysis of Analog Circuits (SAMS)

BMBF Cluster Project (01.11.2003-31.10.2006)

  • Fast Evaluation of Structural Variants
Design and Design Methodology of Embedded Systems (SPP1040)

DFG Priority Programme 1040 (1997-2004)

  • Simulation-based test design for mixed-signal systems
Analogue enhancements for a system to silicon automated design (ANASTASIA+)

BMBF Cluster Project (01.12.2000-31.12.2002)

  • Sizing of Analog Circuits (with Infineon Technologies)