Due to long production and supply chains, circuit designs are prone to theft and manipulation. Logic locking inserts a locking key into the circuit netlist to secure them against these risks. However, so called SAT-based attacks, which check the satisfiability of netlists, were developed to extract the locking keys again.

This work should create a better understanding of sequential SAT-based attacks and extend them towards further applications.

Please contact me to get more information about the topic and the aim of this work.

References:

• Subramanyan, P.; Ray, S. & Malik, S. Evaluating the security of logic encryption algorithms 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2015, 137-143

• El Massad, M.; Garg, S. & Tripunitara, M. Reverse engineering camouflaged sequential circuits without scan access 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017, 33-40

A finite state machine can be represented in several different ways. There is no one right solution. Designers make use of this fact to optimize power, area, or performance.

This work should first create a better understanding of what the limits of the representation of state machines are. Second, these findings should be interpreted in relation to various context.

Please contact me to get more information about the topic and the aim of this work.

References:

• Hartmanis, J. Symbolic analysis of a decomposition of information processing machines Information and Control, Elsevier, 1960, 3, 154-178
• Shelar, R. S.; Desai, M. P. & Narayanan, H. Decomposition of finite state machines for area, delay minimization Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No. 99CB37040), 1999, 620-625