Obfuscation of sequential circuits targets the protection of finite state machines. There exist different approaches to achieve this, like modifying the state machine on RTL level or modifying the corresponding flip-flops on gate-level [1]. A metric can be used to evaluate the success of an obfuscation technique and make it comparable to other methods. Due to the wide variety of sequential obfuscation methods, there are no uniform and very few metrics at all.

This work should analyze existing metrics in terms of how well they can be generalized and thus applied to as many obfuscation techniques as possible. In addition, the work should develop an improved metric.

Please contact me to get more information about the topic and the aim of this work.

References:

• [1] Kamali, Hadi Mardani, et al. "Advances in Logic Locking: Past, Present, and Prospects." Cryptology ePrint Archive (2022).
• R. S. Chakraborty and S. Bhunia, "HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493-1502, Oct. 2009, doi: 10.1109/TCAD.2009.2028166.

Obfuscation of sequential circuits targets the protection of finite state machines. There exist different approaches to achieve this, like modifying the state machine on RTL level or modifying the corresponding flip-flops on gate-level [1]. A metric can be used to evaluate the success of an obfuscation technique and make it comparable to other methods. Due to the wide variety of sequential obfuscation methods, there are no uniform and very few metrics at all.

This work should analyze existing metrics in terms of how well they can be generalized and thus applied to as many obfuscation techniques as possible. In addition, the work should develop an improved metric.

Please contact me to get more information about the topic and the aim of this work.

References:

• [1] Kamali, Hadi Mardani, et al. "Advances in Logic Locking: Past, Present, and Prospects." Cryptology ePrint Archive (2022).
• R. S. Chakraborty and S. Bhunia, "HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493-1502, Oct. 2009, doi: 10.1109/TCAD.2009.2028166.

Due to long production and supply chains, circuit designs are prone to theft and manipulation. Logic locking inserts a locking key into the circuit netlist to secure them against these risks. However, so called SAT-based attacks, which check the satisfiability of netlists, were developed to extract the locking keys again.

This work should create a better understanding of sequential SAT-based attacks and extend them towards further applications.

Please contact me to get more information about the topic and the aim of this work.

References:

• Subramanyan, P.; Ray, S. & Malik, S. Evaluating the security of logic encryption algorithms 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2015, 137-143

• El Massad, M.; Garg, S. & Tripunitara, M. Reverse engineering camouflaged sequential circuits without scan access 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017, 33-40