Franz Biersack, M.Sc.

Due to the rising number of sensors and actuators in modern cars, aimed at enabling features like autonomous dring or car-to-car communication, the on-board electrical/electronic (E/E) architecture is transitioning from the established domain-based design to the new zonal structure. There, each zone is assigned a high-performance zone module tasked with processing the data of all devices within its area. To develop next-generation SoCs and load balancer designs for efficiently distributing and processing the whole spectrum of accumulated workloads, a precise understanding of the sensors and actuators present on the automotive network, as well as the resulting compute tasks and their associated workload is required.

The goal of this seminar topic hence is to compile an overview of processing tasks for upcoming zonal compute nodes, along with a rough expectation of their occurence and required number of instructions.

Multi-Core Processors find their way into more and more application domains and allow for the parallel execution of multiple tasks which are independent from each other. Especially in areas like vehicle networks or wearable computing, not only processing performance, but also energy efficiency is of high importance. To save power during periods of low processing demand, Dynamic Voltage and Frequency Scaling (DVFS) is a mechanism to adaptively scale the clock frequency and supply voltage. Modern CPUs even allow for individual frequency and voltage configurations per CPU core. And while the discrete voltage and clock levels might be set by the used CPU design, the algorithm deciding on when to increase or decrease these metrics can sometimes be freely customized by the user.

The goal of this seminar topic is to investigae state of the art approaches for high efficiency DVFS scaling algorithms.

Multi-Core Processors find their way into more and more application domains and allow for the parallel execution of multiple tasks which are independent from each other. Especially in areas like vehicle networks or wearable computing, not only processing performance, but also energy efficiency is of high importance. To save power during periods of low processing demand, Dynamic Voltage and Frequency Scaling (DVFS) is a mechanism to adaptively scale the clock frequency and supply voltage. Modern CPUs even allow for individual frequency and voltage configurations per CPU core. And while the discrete voltage and clock levels might be set by the used CPU design, the algorithm deciding on when to increase or decrease these metrics can sometimes be freely customized by the user.

The goal of this seminar topic is to investigae state of the art approaches for high efficiency DVFS scaling algorithms.

The Algorand protocol is an environmentally friendly Blockchain technology based on the Proof-of-Stake (POS) consensus mechanism. It represents a new platform for smart contracts trying to solve the blockchain trilemma consisting of scalability, decentralization and security. As part of the ACE-SUPPRA project (Security, Usability, Performance, and Privacy Research in Algorand) we are investigating ways to accelerate the forwarding and broadcasting of Algorand messages throughout the blockchain network with the help of SmartNIC-based HW accelerators to increase the achievable transmission throughput and decrease latencies as well as power consumption.

To this end, the goal of this master thesis is to develop an extension of an existing packet reception, forwarding and delivery SmartNIC design to detect and relay Algorand transaction, block proposal, voting and consensus messages to a given set of network peers. The implementation will require an Algorand message detection entity consisting of a modified packet header parser and a Match-Action-Table. Furthermore, a PCIe-based configuration module for communicating with an attached host PC will be necessary to receive updates on new TCP connections and the IP addresses of the current peer list. The design will also encompass a high priority and bulk broadcast queue for Algorand messages alongside a suitable egress scheduler as well as a message memory and broadcast module for the transmission to four connected peers. Finally, a Packetizer unit will have to be designed, assembling TCP/IP packets and Algorand messages out of multiple Ethernet frames after reception, and vice versa also splitting messages into individual Layer 2 frames prior to their transmission.

Towards this goal you will complete the following tasks:
•    Research existing methods for relaying and broadcasting blockchain messages
•    Implement the design on the NetFPGA-SUME or AMD Alveo U55C prototyping platform
•    Compare and evaluate the implementation with the SW-based Golang implementation of Algorand
•    Document your work in a written thesis report and present your work in a presentation

To successfully complete this project, you should already have the following skills and experiences.
•    Project Laboratory IC-Design or equivalent course
•    Good knowledge about Verilog or VHDL
•    Xilinx Vivado Design Suite and Synopsys VCS / Mentor Graphics ModelSim (tools will be provided)
•    Self-motivated and structured work style