Franz Biersack, M.Sc.

Research Associate

Technical University of Munich
TUM School of Computation, Information and Technology
Chair of Integrated Systems
Arcisstr. 21
80290 München
Germany

Phone: +49.89.289.23869
Fax: +49.89.289.28323
Building: N1 (Theresienstr. 90)
Room: N2138
Email: franz.biersack@tum.de

Curriculum Vitae

• Since Nov. 2018, Doctoral candidate at LIS
• 2018, M.Sc., Electrical and Computer Engineering, Technische Universität München
  Master Thesis: "Implementation of an Image Processing Algorithm" at Airbus Defence and Space
• 2016, B.Eng., Electrical Engineering and Information Technology, Ostbayerische Technische Hochschule Regensburg
  Bachelor Thesis: "Development of the Hardware Concept of a Display Timing Analyzer" at Continental Engineering Services
  Intern and working student during the studies at Continental Engineering Services
• 2012, Intern at PCO

Teaching

Industry 4.0 Laboratory (Bachelor degree laboratory, since SS19)

Digital Circuits (Bachelor degree lecture, since WS19/20)

Supervised Theses

• Implementation of a SmartNIC-Based Hardware Accelerator for Algorand Relay Nodes to Broadcast Blockchain Messages
  (Master Thesis, Markus Hörmann, 2024)
• Design and Implementation of a Graphical User Interface for an Open-Source FPGA-Based Network Tester
  (Working Student, Markus Absmann, 2024)
• Extension of a Load Balancer Hardware Implementation on the NetFPGA-SUME Platform for Priority-Awareness
  (Working Student, Fabiana Lotter, 2024)
• Configurable Pinning of Flow Priorities to CPU Cores for a Simulation Framework of a SmartNIC-based Hardware Load Balancer
  (Bachelor Thesis, Fabiana Lotter, 2023)
• Design and Implementation of a Power Consumption Model for a Network Simulation Framework with Multi-Core Compute Nodes
  (Bachelor Thesis, Markus Absmann, 2023)
• Modeling and Simulation of Automotive E/E Architecture
  (External Master Thesis, Chengxi Li, 2023)
• Design and Evaluation of a Hardware-based Packet Timestamping Mechanism in a Dynamic Load Balancer for NICs
  (Master Thesis, Diana Leichte, 2022)
• Hardware Implementation of a Priority-Based Packet Queuing and Scheduling Mechanism
  (Bachelor Thesis, Berke Karakin, 2021)
• Finding the Best Sets of C Compiler Optimization Options for Sensorless Field-Oriented Motor Control on an ARM Cortex-M3 Based Processor
  (External Bachelor Thesis, Benedikt Witteler, 2021)
• Correction of Packet Delay Variation for Time Sensitive Networking with Frame Preemption on a Xilinx FPGA
  (External Master Thesis, Tarik Ibrahimpašić, 2020)
• Testautomatisierung im FPGA Jenkins Build Flow mit dem Radio Communication Tester R&S ® CMX500
  (External Research Internship, Daniela Lutz, 2020)
• Evaluation of Various Non-Transparent PCIe Bridge Configurations between Two x86 Processors
  (External Bachelor Thesis, Chengxi Li, 2020)
• Evaluation of an embedded PCI Express Smart Interconnect concept within a large scaled automotive E/E platform
  (External Master Thesis, Andrea Nicholas Beretta, 2019)