Digital System Design with VHDL
| Lecturer (assistant) | |
|---|---|
| Number | 0000005077 |
| Type | lecture with integrated exercises |
| Duration | 4 SWS |
| Term | Summer semester 2026 |
| Language of instruction | Deutsch,English |
| Position within curricula | See TUMonline |
Admission information
Description
The return of assignments must be via Moodle according to schedule. Groups with up to 4 students may be formed to build the model. The contribution of each student to the model must be documented in the model.
Delivery deadlines to be announced
The simulation of the models is essential, the tool Vivado from Xilinx can (and must) be downloaded for that purpose.
Models will be reviewed and contribute overall 50% to the final grade.
The content of the lecture covers the Hardware description languages VHDL and SystemC, design methodology with VHDL and SystemC, VHDL/SystemC modeling, VHDL/SystemC simulation and VHDL register-transfer synthesis. There will be computer lab exercises in VHDL/SystemC modeling, automatic synthesis and selected synthesis methods.
Hardware description language VHDL and SystemC, design methodology with VHDL and SystemC, VHDL/SystemC modeling, VHDL/SystemC simulation and VHDL/SystemC synthesis, methods of logic synthesis, register-transfer synthesis and high-level synthesis; computer lab exercises in VHDL/SystemC modeling, automatic synthesis and selected synthesis methods.
Delivery deadlines to be announced
The simulation of the models is essential, the tool Vivado from Xilinx can (and must) be downloaded for that purpose.
Models will be reviewed and contribute overall 50% to the final grade.
The content of the lecture covers the Hardware description languages VHDL and SystemC, design methodology with VHDL and SystemC, VHDL/SystemC modeling, VHDL/SystemC simulation and VHDL register-transfer synthesis. There will be computer lab exercises in VHDL/SystemC modeling, automatic synthesis and selected synthesis methods.
Hardware description language VHDL and SystemC, design methodology with VHDL and SystemC, VHDL/SystemC modeling, VHDL/SystemC simulation and VHDL/SystemC synthesis, methods of logic synthesis, register-transfer synthesis and high-level synthesis; computer lab exercises in VHDL/SystemC modeling, automatic synthesis and selected synthesis methods.
Prerequisites
Basis knowledge of digital design and programming language (C or C++) is absolutely necessary.
Teaching and learning methods
Exemplary learning is used. With help of an MIPS2 subsystem the requirements will be motivated, represented and generalized. The understanding will be deepened by team work under industrial techniques.
Following media will be used:
- Presentations as handouts
- Case studies
- Template solutions
Following media will be used:
- Presentations as handouts
- Case studies
- Template solutions
Links
Bachelorbereich: BSc-EI, BSES, BSEDE
| SS | Diskrete Mathematik für Ingenieure (BSEI, EI00460) (Schlichtmann) | |
| WS | Discrete Mathematics for Engineers (BSEDE) (Schlichtmann) | |
| WS | Grundlagen der Elektrotechnik I (BSES, EI10014) (Schlichtmann) | |
| WS | SS | Entwurf digitaler Systeme mit VHDL u. System C (BSEI, EI0690) (Ecker) |
| SS | Entwurfsverfahren für integrierte Schaltungen (BSES, EI43811) (Schlichtmann) | |
| SS | Schaltungssimulation (BSEI, EI06691) (Schlichtmann/ Leibl) |
Masterbereich: MSc-EI, MSCE, ICD
| SS | Advanced Topics in Communication Electronics (MSCE, EI79002) | ||
| SS | Electronic Design Automation (MSMCD, MSCE, MSEI, EI70610) (Schlichtmann, Tseng) | ||
| WS | Design Methodology and Automation (ICD) (Schlichtmann) | ||
| WS | Embedded System Design for Machine Learning (MSCE, MSEI, EI71040) (Ecker) | ||
| SS | Simulation and Optimization of Analog Circuits (ICD) (Gräb) | ||
| SS | Mixed Integer Programming and Graph Algorithms in Engineering Problems (MSMCD, MSCE, MSEI, EI71059) (Tseng) | ||
| WS | SS | Numerische Methoden der Elektrotechnik (MSEI, EI70440) (Schlichtmann/ Truppel) | |
WS WS | SS | Seminar VLSI-Entwurfsverfahren (MSEI, EI7750) (Schlichtmann) Seminar on Topics in Electronic Design Automation (MSMCD, MSCE, EI77502) (Schlichtmann) | |
| WS | SS | Synthesis of Digital Systems (MSCE, MSEI, EI70640) (Geier) | |
| WS | Testing Digital Circuits (MSMCD, MSCE, MSEI, EI50141) (Otterstedt) | ||
| WS | SS | VHDL System Design Laboratory (MSCE, MSEI, EI7403) (Schlichtmann) | |
| WS | SS | HDL Chip Design Laboratory (MSMCD, CIT431016) (Schlichtmann) |
BSES: Bachelor of Science Engineering Science (TUM-ED)
BSEDE: Bachelor of Science in Electronics and Data Engineering (TUM-Asia)
ICD: Master of Science in Integrated Circuit Design (TUM-Asia)
MSMCD: Master of Science in Microelectronics and Chip Design (TUM)
MSCE: Master of Science in Communications Engineering (TUM)
MSEI: Master of Science in Elektrotechnik und Informationstechnik
BSEI: Bachelor of Science in Elektrotechnik und Informationstechnik