Design Methods for Integrated Circuits (MSE)
| Lecturer (assistant) | |
|---|---|
| Number | 0000001969 |
| Type | lecture with integrated exercises |
| Duration | 3 SWS |
| Term | Summer semester 2026 |
| Language of instruction | Deutsch |
| Position within curricula | See TUMonline |
Admission information
Description
Logic Synthesis: binary Boolean functions, optimization of combinational circuits (two-level, multi-level), FSMs, optimization of sequential circuits.
Logic Simulation: event-driven simulation, modelling and simulation using VHDL.
Testing of digital circuits: fault diagnosis; fault covering table; test pattern generation in combinational circuits; test pattern generation in sequential circuits; design for testability.
Logic Simulation: event-driven simulation, modelling and simulation using VHDL.
Testing of digital circuits: fault diagnosis; fault covering table; test pattern generation in combinational circuits; test pattern generation in sequential circuits; design for testability.
Prerequisites
Module "Principles in Electrical Technology I".
Familiarity with discrete mathematics is beneficial, but not required.
Familiarity with discrete mathematics is beneficial, but not required.
Teaching and learning methods
Both in lecture and in tutorial, the lecturer presents the material to the students. Some interactive questions / discussions will be held. In the tutorial, the students will in addition work on problems on their own.
Media
Primarily notes on blackboard and / or tablet PC;
PowerPoint slides (primarily for introduction of new sections).
Lecture materials will be provided to the students.
Possibly online problems will be used to support independent learning by the students.
Media
Primarily notes on blackboard and / or tablet PC;
PowerPoint slides (primarily for introduction of new sections).
Lecture materials will be provided to the students.
Possibly online problems will be used to support independent learning by the students.
Links
Bachelorbereich: BSc-EI, BSES, BSEDE
| SS | Diskrete Mathematik für Ingenieure (BSEI, EI00460) (Schlichtmann) | |
| WS | Discrete Mathematics for Engineers (BSEDE) (Schlichtmann) | |
| WS | Grundlagen der Elektrotechnik I (BSES, EI10014) (Schlichtmann) | |
| WS | SS | Entwurf digitaler Systeme mit VHDL u. System C (BSEI, EI0690) (Ecker) |
| SS | Entwurfsverfahren für integrierte Schaltungen (BSES, EI43811) (Schlichtmann) | |
| SS | Schaltungssimulation (BSEI, EI06691) (Schlichtmann/ Leibl) |
Masterbereich: MSc-EI, MSCE, ICD
| SS | Advanced Topics in Communication Electronics (MSCE, EI79002) | ||
| SS | Electronic Design Automation (MSMCD, MSCE, MSEI, EI70610) (Schlichtmann, Tseng) | ||
| WS | Design Methodology and Automation (ICD) (Schlichtmann) | ||
| WS | Embedded System Design for Machine Learning (MSCE, MSEI, EI71040) (Ecker) | ||
| SS | Simulation and Optimization of Analog Circuits (ICD) (Gräb) | ||
| SS | Mixed Integer Programming and Graph Algorithms in Engineering Problems (MSMCD, MSCE, MSEI, EI71059) (Tseng) | ||
| WS | SS | Numerische Methoden der Elektrotechnik (MSEI, EI70440) (Schlichtmann/ Truppel) | |
WS WS | SS | Seminar VLSI-Entwurfsverfahren (MSEI, EI7750) (Schlichtmann) Seminar on Topics in Electronic Design Automation (MSMCD, MSCE, EI77502) (Schlichtmann) | |
| WS | SS | Synthesis of Digital Systems (MSCE, MSEI, EI70640) (Geier) | |
| WS | Testing Digital Circuits (MSMCD, MSCE, MSEI, EI50141) (Otterstedt) | ||
| WS | SS | VHDL System Design Laboratory (MSCE, MSEI, EI7403) (Schlichtmann) | |
| WS | SS | HDL Chip Design Laboratory (MSMCD, CIT431016) (Schlichtmann) |
BSES: Bachelor of Science Engineering Science (TUM-ED)
BSEDE: Bachelor of Science in Electronics and Data Engineering (TUM-Asia)
ICD: Master of Science in Integrated Circuit Design (TUM-Asia)
MSMCD: Master of Science in Microelectronics and Chip Design (TUM)
MSCE: Master of Science in Communications Engineering (TUM)
MSEI: Master of Science in Elektrotechnik und Informationstechnik
BSEI: Bachelor of Science in Elektrotechnik und Informationstechnik