24.01.2025 Microfuidic chips: recent advances, critical strategies in design, applications and future perspectives Supervisor:Yushen Zhang
24.01.2025 Software Performance Simulation with gem5 Supervisor:Conrad Foik
24.01.2025 Arithmetic Code-based Error Detection for Reliable Computing Supervisor:Johannes Geier
17.01.2025 Thermal Modeling of Integrated Circuits on Architecture Level Supervisor:Philipp Fengler
17.01.2025 Generally Applicable Power Estimation Methodologies for Accelerators Supervisor:Philipp Fengler
17.01.2025 Thermal Modeling of Integrated Circuits on Architecture Level Supervisor:Philipp Fengler
17.01.2025 Generally Applicable Power Estimation Methodologies for Accelerators Supervisor:Philipp Fengler
2024
Bachelor's Theses
18.12.2024 Marcel Manh Hieu Do Development of Microfluidic Mold Design Mode for Flui3d Supervisor:Yushen Zhang
11.10.2024 Efficient Neural Network-Based ASIC Power Estimation with Linear Regression Supervisor:Philipp Fengler
24.09.2024 Enhancement of Artificial Netlist Generation for Power Modeling Supervisor:Philipp Fengler
17.09.2024 Dragan Ra?eta Development of Multi-Layer 3D-Printed Microfluidics: Design Synthesis with Timing and Volumetric Considerations Supervisor:Yushen Zhang
17.09.2024 Laurin Rippel Development of an Online ONoC (Optical Network-on-Chip) Design Platform Supervisor:Yushen Zhang
06.05.2024 Automatic Extraction of Intermediate Performance Values via SPICE Supervisor:Markus Leibl
02.04.2024 GPU-Acceleration for Event-Driven Gate-Level Simulation Supervisor:Philipp Fengler
12.01.2024 Automated Optimization of a Library of Operational Amplifiers Supervisor:Markus Leibl
Master's Theses
01.10.2024 Implementation and Evaluation of RISC-V Vector Half-Precision Floating-Point Extension for Machine Learning Inference Supervisor:Philipp van Kempen
24.09.2024 Performance Models of a RISC-V Memory Architecture Supervisor:Conrad Foik
15.05.2024 Extending An RTL Fault Injection Platform for Hardware Accelerated ML Workloads Supervisor:Johannes Geier
08.05.2024 Timothée Felicio Design Synthesis of Multi-Layer Microfluidics A Deep-Learning Approach Supervisor:Yushen Zhang
30.04.2024 Automated Instruction Generation for Instruction Set Architecture Exploration Supervisor:Philipp van Kempen
30.04.2024 Analysis of Branch Prediction Schemes for the CVA6 Processor Supervisor:Conrad Foik
15.03.2024 Enable Reuse of UVM-SystemVerilog Verification Components in cocotb/PyUVM Supervisor:Conrad Foik, Infineon Technologies
01.02.2024 Minxing Wang Routing Strategy for Multi-Layer Microfluidic Devices Using ILP Supervisor:Yushen Zhang
23.01.2024 Bo Liu Software Implemented Hardware Fault Tolerance for TinyML Applications in the Presence of Faults in Microarchitecture Supervisor:Johannes Geier
09.01.2024 Comparison of Machine Learning Methods for Opaque Black-Box Power Modeling Supervisor:Philipp Fengler
Research Internships (Forschungspraxis)
01.08.2024 Virtual Prototyping of a RISC-V Based SoC for IoT-ML Applications Supervisor:Conrad Foik
22.03.2024 Louis Dickgießer Exploring large language models for microfluidic usage Supervisor:Yushen Zhang
01.03.2024 Logic Level Based Unit Delay Simulation Supervisor:Philipp Fengler
26.02.2024 Verification of Model Outputs in TinyML Deployment Flow Supervisor:Philipp van Kempen
Seminars
05.07.2024 Low Power Techniques for Large Language Models Supervisor:Richard Petri
05.07.2024 Challenges and Benefits of Mixed-Precision Integer-Quantization for Embedded Machine Learning Applications Supervisor:Philipp van Kempen
05.07.2024 Power Modeling on Electronic System Level Supervisor:Philipp Fengler
05.07.2024 Novel Quantum Algorithms to Minimize Switching Functions Based on Graph Partitions Supervisor:Philipp Fengler
25.01.2024 Data learning techniques and methodology for Fmax prediction Supervisor:Zhidan Zheng
25.01.2024 Comparison of ARM and RISC-V ISA Supervisor:Conrad Foik, Wolfgang Ecker, Sebastian Prebeck (Infineon)
25.01.2024 Comparison of ARM DSP and RISC-V Packed Instructions Supervisor:Conrad Foik, Wolfgang Ecker, Sebastian Prebeck (Infineon)
25.01.2024 PULP: A Solution to Low Power Parallel Processing Supervisor:Philipp van Kempen
25.01.2024 Rule-based Synthesis with Bluespec SystemVerilog Supervisor:Conrad Foik, Robert Kunzelmann (Infineon)
25.01.2024 Automatic Dataset Generation for EDA Applications Supervisor:Philipp Fengler
25.01.2024 Automatic Dataset Generation for EDA Applications Supervisor:Philipp Fengler
25.01.2024 Machine Learning for SDC Probability Estimation Supervisor:Johannes Geier
25.01.2024 Comparison of ARM and RISC-V Instruction Encoding Supervisor:Conrad Foik, Wolfgang Ecker, Sebastian Prebeck (Infineon)
Student Assistant Jobs
31.03.2024 Improve performane of muRISCV-NN kernel s Supervisor:Philipp van Kempen
2023
Bachelor's Theses
06.11.2023 Quantitative Fault Coverage Analysis of Analog Mixed-Signal Integrated Circuits Using Fault Effect Modeling for Functional Safety Supervisor:Johannes Geier, Kurt Neugebauer (NXP)
11.10.2023 Development of a Proxy-Server for Parallel Operation of Multiple XCP Applications Supervisor:Johannes Geier, David Maier (BMW)
08.09.2023 Automatic Integration of Custom RISC-V Instructions into LLVM Toolchain Supervisor:Philipp van Kempen
30.03.2023 Zhiyi Pan Emerging Fabrication Method: 3D-Printing's Applications in Microfluidics Supervisor:Yushen Zhang
23.02.2023 Open-Source ASIC Design Flow-based Dataset Generation for Power Modeling Supervisor:Philipp Fengler
12.01.2023 Verifying the Controller Code of a Power Inverter for Hardware Testing Supervisor:Helmut Gräb
Master's Theses
14.12.2023 System Study on Embedded RISC-V Multi-Core Power Controller Solution Supervisor:Conrad Foik, Infineon Technologies
30.11.2023 Omar Elkhouly Generation and Verification of ETISS Simulator for CORE-V Instruction Set Extension Supervisor:Philipp van Kempen
27.11.2023 Yi-Tun Wang Evaluation of Hardware Loop Acceleration of Embedded ML Inference on RISC-V Platforms Supervisor:Philipp van Kempen
22.09.2023 Exploring Formal Verification Methods on Image Signal Processing Circuits Supervisor:Conrad Foik, Apple
15.08.2023 Shuo Wu Microfluidics Design Automation based on Deep Reinforcement Learning in Parameterized Action Space Supervisor:Yushen Zhang
01.06.2023 Konstantinos Asimakopoulos Runtime Switch Behavior for a Multi-level RISC-V Register Transfer Level (RTL) to Instruction Set Fault Injection Simulator Supervisor:Johannes Geier
Research Internships (Forschungspraxis)
09.11.2023 Data-Driven Power Modeling of Black-Box Sequential Circuits Supervisor:Philipp Fengler
10.10.2023 Performance Estimator for RISC-V Packed Extension Supervisor:Philipp van Kempen
01.10.2023 Performance Models for a RISC-V Memory Architecture Supervisor:Conrad Foik
11.09.2023 Performance improvements for FPGA based Co-Emulation Supervisor:Johannes Geier, Philipp Kadletz (pkadletz@apple.com) (Apple)
11.09.2023 Optimizing Data Density for Co-emulation based Infrastructures Supervisor:Johannes Geier, Philipp Kadletz (pkadletz@apple.com) (Apple)
20.08.2023 Reimplementation of Checkerboard Context Model for Efficient Learned Image Compression Supervisor:Nikolai Körber
07.06.2023 Design, Optimization and Evaluation of an Operational Amplifier Supervisor:Markus Leibl
01.05.2023 Samyuktha Sena Indrasena Microfluidic Control-Pump Supervisor:Yushen Zhang
01.03.2023 Alternative Automated Graph Extraction for GAT-based Switching Activity Estimation Supervisor:Philipp Fengler
Internships
11.08.2023 Development of an Automized Testbench and Simulation Interface for Operational Amplifiers Supervisor:Markus Leibl
06.07.2023 Development of an Automized Testbench and Simulation Interface for Operational Amplifiers Supervisor:Markus Leibl
11.05.2023 Antonius Adisoemarta STL library Design for Javascript Supervisor:Yushen Zhang
06.05.2023 Yi Yue Development of software modules (C++/Qt) for simulation methods for impulse-based rigid body dynamics Supervisor:Yushen Zhang, RNA Digital GmbH
Seminars
06.10.2023 Dynamic Neural Network Supervisor:Wenhao Sun
14.07.2023 Fast Cycle-Accurate Simulators for RISC Processors Supervisor:Conrad Foik
30.06.2023 A Memetic Algorithm for VLSI Floorplanning Supervisor:Mengchu Li
30.06.2023 A Survey: Analog Circuit Sizing using Machine Learning Methods Supervisor:Markus Leibl
30.06.2023 Checkpointing Techniques for Fast Forwarding RTL Fault Injection Simulations Supervisor:Johannes Geier
20.01.2023 Xuanyu Yi Hardware-based Approaches to Soft Error Correction and Detection in Combinational and Sequential Logic Supervisor:Johannes Geier
20.01.2023 GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors Supervisor:Conrad Foik
20.01.2023 Using Graph Neural Networks for Timing Estimation: A Survey Supervisor:Daniela Sanchez Lopera, Infineon Technologies AG
20.01.2023 A Novel Algorithm for Reducing the Power Loss of Routing Paths in ONoCs Supervisor:Zhidan Zheng
Student Assistant Jobs
30.09.2023 Extending support for RISC-V Packed Extension in ETISS Supervisor:Philipp van Kempen
30.06.2023 Enable Debugging of RISC-V Vector Instructions using GDB within ETISS simulations Supervisor:Philipp van Kempen
31.03.2023 Integrate PULP-Platform Cores in MLonMCU Deployment Flow Supervisor:Philipp van Kempen
2022
Bachelor's Theses
17.10.2022 Xianer Chen Development of an interactive design platform for microfluidic IP modules Supervisor:Yushen Zhang
12.10.2022 Generation of area-optimized ALUs for RISC-V CPUs Supervisor:Conrad Foik, Infineon Technologies
05.08.2022 Semihosting for the ETISS Instruction Set Simulator Supervisor:Karsten Emrich
25.07.2022 Design and Implementation of a Test Environment for Functional Verification of Developed Software Libraries Supervisor:Conrad Foik, Infineon
22.07.2022 Xinwei Li Performance Estimation of Analog Circuits using Structural Similarity and Neural Networks Supervisor:Markus Leibl
28.12.2022 Automated Multi-Camera Calibration in Sparse-Feature Environments Supervisor:Helmut Gräb
09.12.2022 Modeling Advanced CPU Pipeline Features for Fast and Accurate Performance Simulation of a RISC-V Microprocessor Supervisor:Conrad Foik
28.11.2022 Influence of Open-Source Process Design Kits on Hardware Reverse Engineering and Trusted Hardware Supervisor:Helmut Gräb
20.10.2022 Philipp Nassua Multi-process Framework for Output-oriented Hardware Fault Attack Simulations at Register Transfer Level Supervisor:Johannes Geier
15.10.2022 Lasse Urban Development of a Runtime Switch Behavior for a Multi-level RISC-V Instruction Set to Register Transfer Fault Injection Simulator Supervisor:Johannes Geier
06.09.2022 Post-Physical Design Power Modeling for ASIC Development by Data-Driven Approaches Supervisor:Philipp Fengler
28.06.2022 Uncertainty-Based Scene-Independent Radar Tracking with Meta Reinforcement Learning Supervisor:Helmut Gräb
02.06.2022 Johannes Sanwald Implementation of a Memory Management Unit in a RISC-V Instruction Set Simulator Supervisor:Johannes Geier, Karsten Emrich
19.05.2022 Decision-Tree-based Stimuli Generation for Coverage-driven RT-Level Verification Supervisor:Conrad Foik, Apple
24.03.2022
Supervisor:Helmut Gräb
17.02.2022 Xiaolin Ma Developing an interactive web user interface for designing 3D-printed microfluidic devices Supervisor:Yushen Zhang
Research Internships (Forschungspraxis)
21.12.2022 MoChirp - A Simple RISC-V Microcontroller with Hardware- Accelerated FFT for Radar Processing as Case Study for Building Custom SoCs in an Open Ecosystem Supervisor:Johannes Geier, Motius
14.10.2022 Srinidhi Hari Prasad Formal Side Channel Verification of Masked Hardware Implementations Using Coco-Alma Supervisor:Johannes Geier, Ralph Nyberg (Infineon (IFAG CSS DSI D CI VER))
28.09.2022 Performance Estimation on RISC-V ISS using RI5CY Supervisor:Conrad Foik
21.09.2022 Bo Liu Exploring the Pipeline Behavior of a RISC-V Core under Register Transfer Level Fault Attack Simulation Supervisor:Johannes Geier
13.09.2022 Analog Fault Injection/Safety Analysis Supervisor:Helmut Gräb
24.06.2022 Cosine Similarity and Euclidean Distance-based OOD Detection Supervisor:Helmut Gräb
15.05.2022 Automatisierte Verdrahtung und Platzierung elektrischer Komponenten im 3D-CAD-Schaltschrank Supervisor:Helmut Gräb
02.05.2022 Examination of the OpenROAD and Proprietary Design Environment with Discussion about Similarities and Differences Supervisor:Helmut Gräb
01.04.2022 Reconstruction Regularized Deep Metric Learning for Multi-label Image Classification Supervisor:Helmut Gräb
31.03.2022 Algorithm Based Fault Tolerance for Embedded Case Studies Supervisor:Uzair Sharif
Internships
21.10.2022 Automatisierung des Lichtleiterhandlings in Kombination mit Verbesserungen des Workflows und der Qualität der Produkte in Bezug auf Electro-Static-Discharge Supervisor:Helmut Gräb
17.05.2022 Implementation of a Switching Activity Estimator in the PyMTL3 Framework Supervisor:Philipp Fengler
08.05.2022 Test und Absicherung von Komponenten im Automotive-Bereich Supervisor:Helmut Gräb
08.04.2022 Entwicklung einer grafischen Benutzeroberfläche zur Funktionsprüfung von Haltebremsen an einer numerischen Steuerung Supervisor:Helmut Gräb
Seminars
15.07.2022 Survey: Power Estimation on the Electronic System Level Supervisor:Conrad Foik
15.07.2022 Semihosting in instruction set simulators and virtual platforms Supervisor:Karsten Emrich
15.07.2022 Modern approaches for heuristic algorithms in network architecture searchs (nas) Supervisor:Conrad Foik
15.07.2022 Reinforcement Learning for Digital Electronic Design Automation Supervisor:Daniela Sanchez Lopera
15.07.2022 Power-Performance-Area Prediction using Machine Learning Supervisor:Daniela Sanchez Lopera
15.07.2022 Graph Placement Methodologies for Fast Chip Design Supervisor:Philipp Fengler
28.02.2022 Soft error resilience for tinyML systems Supervisor:Uzair Sharif
28.01.2022
Supervisor:Conrad Foik
28.01.2022 Comparison of countermeasures against single glitch fault attacks: Compiler based Techniques vs Algorithm based Techniques Supervisor:Johannes Geier
28.01.2022 System-on-Chip Performance Prediction Using Machine Learning Techniques Supervisor:Tobias Kilian
21.01.2022 Tobias Genzinger Detection of Transient Faults Detection by Control Flow Checking with Signature Monitoring Supervisor:Johannes Geier
