Here you can find all available student positions of our chair. We offer master theses, bachelor theses, research internships, industry internships and interdisciplinary projects. If you cannot find a suitable offering, please contact one of our research members. To find more information about the research topics of our chair you can visit Research. Furthermore, we offer seminar topics.

 

Bachelor's Theses

Dataset Generation for Graph Attention Network-based Power Estimation

Description

In System on Chip (SoC) design, power consumption gets increasingly important (e.g. due to increasing complexity of the devices and contrary, due to the growing number of mobile applications). Although precise gate-level simulation methods exist, they are often not feasible for larger designs. Therefore, less accurate, but faster methods have been developed [1]. For dynamic power dissipation, the switching activity of a design is crucial (beside technological parameters). Here, already approaches for its estimation based on Machine Learning, namely Graph Neural Networks (GNN), have been developed [2]. 

But, existing approaches require detailed information about the structure of a circuit (e.g. the gate level netlist) for exact power estimation. This information may not be always available (e.g. in early design stages or in black-box IP blocks). Therefore, approaches to achieve a exact power estimation with limited knowledge would be appreciated. In previous work, a framework for power estimation based on Graph Attention Neural Networks (GAT) has been developed to obtain power estimations based on only the primary input and output signals of a design and its relationships, modelled as graphs.

In this project, a dataset with multiple reference designs (e.g. benchmark circuits or open-source cores) should be generated to enable further training of the GAT-based power estimation framework. This includes the selection of appropriate reference designs, their synthesis and physical design in respective tools and the extraction power wavefroms from gate level simulation. Furthermore, a framework for automatic dataset generation may be developed.


[1] NAJM, Farid N.; XAKELLIS, Michael G. Statistical Estimation of the, Switching Activity in VLSI Circuits. VLSI Design, 1998, 7. Jg., Nr. 3, S. 243-254.

[2] ZHANG, Yanqing; REN, Haoxing; KHAILANY, Brucek. GRANNITE: Graph neural network inference for transferable power estimation. In: 2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020. S. 1-6.

 

Prerequisites

  • Experience in Python programming would be beneficial
  • Knowledge in HDLs and CMOS power consumption
  • Interest in the ASIC Development Flow and Machine Learning in EDA
  • Ability to work independently

 

Contact

If you are interested in this topic, please feel free to contact me at:

philipp.fengler@tum.de

Supervisor:

Philipp Fengler

Online Microfluidics Programming Platform

Keywords:
Microfluidics, Lab-On-Chip, Programming
Short Description:
We want to introduce an interactive but intuitive programming platform for microfluidic researchers that do not require any pre-experience with programming.

Description

Microfluidic Large Scale Integration (mLSI) refers to the development of microfluidic chips with thousands of integrated micromechanical valves and control components. This technology is used in many areas of biology and chemistry and is a candidate for replacing today's conventional automation paradigm, which consists of Robots for handling liquids.

 

To enable automated control of mLSI, programming sequence for valve control and fluid inputs is essential. Although, not every researcher, especially biologists or chemists, has programming skills. We want to introduce an interactive but intuitive programming platform for microfluidic researchers that do not require any pre-experience with programming to overcome this problem.

 

This platform provides a visual programming language that allows users to define their needs by dragging and dropping the command blocks into a canvas. A flow simulation will show up on the side when users click on the run. 

Prerequisites

  • Knowledge and experience in web design and web development
  • Good knowledge of HTML5, CSS, JavaScript and PHP (or Java Spring Boot) or the wiliness to learn them
  • Basic knowledge of SQL, jQuery and Vue.js (or other frontend framework) or the wiliness to learn them
  • Solution-oriented thinking

 

Contact

If you are interested in this topic, please send your current transcript along with your CV and a short motivation to one of the supervisors' email:

Yushen.Zhang+Project@TUM.de

Supervisor:

Yushen Zhang

Predictive Maintenance/ Anomaly Detection on the Edge

Description

Anomaly detection plays an important role in many applications scenarios. In the Industrial Internet of Things (IIoT), anomaly detection enables permanent monitoring and evaluation of machine and process data. In this way, machine failures can be predicted at an early stage, thus avoiding malfunctions, and making maintenance processes efficient.

Traditionally, the raw data is sent to centralized servers where large-scale systems perform analytics on the data gathered from all devices. However, this often leads to high network traffic, latency, and privacy issues. The goal of this work is to analyze the extent to which deep learningbased anomaly detection models can be deployed directly to highly resource-constrained devices (MCUs).

Contact

nikolai.koerber@tum.de

Supervisor:

Nikolai Körber

Machine Learning and Neural Networks' Applications in Microfluidics

Short Description:
Neural Network, AI, Machine Learning, Microfluidcs

Description

Machine learning (ML) is taking an important role in our lives these days, which has been widely used in many scenarios. ML methods, including traditional and deep learning algorithms, achieve amazing performance in solving classification, detection, and design space exploration problems.

In recent years, ML for design automation is becoming one of the trending topics and a lot of studies that use ML to improve DA methods have been proposed, which cover almost all the stages in the chip design flow, including design space reduction and exploration, logic synthesis, placement, routing, testing, verification, manufacturing, etc. These ML-based methods have demonstrated impressive improvement compared with traditional methods. In this project, we want to explore and exercise the applications of machine learning and neural networks used for microfluidics design automation.

Prerequisites

  • Knowledge and experience in artificial intelligence and machine learning
  • Good knowledge of Python, Java, or other programming languages and Tensorflow or other ML frameworks or the wiliness to learn them
  • Basic understanding of Generative Adversarial Network or other NN principles
  • Solution-oriented thinking

Contact

If you are interested in this topic, please send your current transcript along with your CV and a short motivation to one of the supervisors' email:

Yushen.Zhang+Project@TUM.de

Supervisor:

Yushen Zhang

Exploring the relationship between weights and accuracy of neural networks

Keywords:
Neural network

Description

In neural networks, some weights are not important to the accuracy of neural networks, indicating that there exists redundancy in neural networks. This redundancy can be used to adjust the shape of weight distributions of neural networks. This adjustment of weight distributions can be achieved by adding penalties in the cost function of neural networks during software training. For example, Figure 1 shows an adjustment of weight distribution by adding penalties during software training.

 

In this bachelor thesis, the tradeoff between the accuracy of neural networks and the shape of weight distributions will be explored. In addition, how the pruning affects this tradeoff will also be explored.

Contact

If you are interested in this topic for bachelor thesis, please contact: 

Dr.-Ing. Li Zhang (grace-li.zhang@tum.de) with your CV and transcripts.

Supervisor:

Li Zhang

Master's Theses

Evaluation of Hardware Loop Acceleration of Embedded ML Inference on RISC-V Platforms

Keywords:
RISCV, Hardware Loops, Zero Overhead Loops, Accelerator, Machine Learning, TVM
Short Description:
Tiny Machine Learning (TinyML) is a research area in the field of machine learning and describes the optimization and inference of ML workloads on edge devices. In contrast to traditional machine learning, TinyML devices are very limited in their processing capability. Zero-overhead loops are a technique which can be used to achieve performance improvements in various data-driven applications on resource constrained targets. This is achieved implementation the checking and increment of the loop counter in hardware which may reduce the inference latency i.e. in ML allocations as less CPU cycles are wasted in these loops.

Description

In this work the design and integration of hardware loop acceleration should be studied in the context of Embedded Machine Learning. The steps of this thesis can be summarized as follows:

  • Survey the current state-of-the are of zero-overhead loops in research (and industry)
  • Introduce the basic knowledge/theory required to understand the concept of hardware loop acceleration
  • Propose and implement an hardware architecture for a simple hardware loop accelerator
  • Integrate your hardware loop acceleration into a RISC-V VP run in the ETISS simulator
  • Produce preliminary benchmarks to compare implementations with and without hardware loop support.
  • Optional: Integrate the hardware loop intrinsics in the TVM ML compiler flow to automatically generate accelerated programs.
  • Optional: Benchmark your zero-overhead loop implementation on various real-world ML models.

Prerequisites

  • Good knownledge on processor architectures (ideally RISC-V)
  • Experience with Embedded Machine Learning e.g. Training (Keras/TensorFlow), Embedded Software Development (C, Assembly) and Hardware Accelerator Design (VHDL/Verilog)
  • Experience with C/C++
  • Optional: Experience with CoreDSL2
  • Optional: Experience with the TVM ML Compiler flow
  • Optional: Experience with the ETISS simulator

Supervisor:

Philipp van Kempen

Automatic Generation of RISC-V Special Instructions in SW Toolchains

Short Description:
In this thesis, a method and implementation should be developed in order to automatically generate patches for the LLVM and GCC toochain from a formal definition of a special instruction.

Description

RISC-V is a new, open instruction set architecture (ISA) that, as a core feature, can be extended with special instructions to customize embedded processors to special applications such as frm the control and machine learning domain.

We already developed a customizable simulator named ETISS, that can quickly evaluate the benefit of special instructions for a given application. Next to the core, also the compiler and assembler support for creating a binary from embedded C code is required by designers to exploit performance benefits of special instructions.

In this thesis, a method and implementation should be developed in order to automatically generate patches for the LLVM and GCC toochain from a formal definition of a special instruction. There are various levels of special instruction support possible in the toolchain, that should be explored within this thesis.

Supervisor:

Online Microfluidics Programming Platform

Keywords:
Microfluidics, Lab-On-Chip, Programming
Short Description:
We want to introduce an interactive but intuitive programming platform for microfluidic researchers that do not require any pre-experience with programming.

Description

Microfluidic Large Scale Integration (mLSI) refers to the development of microfluidic chips with thousands of integrated micromechanical valves and control components. This technology is used in many areas of biology and chemistry and is a candidate for replacing today's conventional automation paradigm, which consists of Robots for handling liquids.

 

To enable automated control of mLSI, programming sequence for valve control and fluid inputs is essential. Although, not every researcher, especially biologists or chemists, has programming skills. We want to introduce an interactive but intuitive programming platform for microfluidic researchers that do not require any pre-experience with programming to overcome this problem.

 

This platform provides a visual programming language that allows users to define their needs by dragging and dropping the command blocks into a canvas. A flow simulation will show up on the side when users click on the run. 

Prerequisites

  • Knowledge and experience in web design and web development
  • Good knowledge of HTML5, CSS, JavaScript and PHP (or Java Spring Boot) or the wiliness to learn them
  • Basic knowledge of SQL, jQuery and Vue.js (or other frontend framework) or the wiliness to learn them
  • Solution-oriented thinking

 

Contact

If you are interested in this topic, please send your current transcript along with your CV and a short motivation to one of the supervisors' email:

Yushen.Zhang+Project@TUM.de

Supervisor:

Yushen Zhang

Predictive Maintenance/ Anomaly Detection on the Edge

Description

Anomaly detection plays an important role in many applications scenarios. In the Industrial Internet of Things (IIoT), anomaly detection enables permanent monitoring and evaluation of machine and process data. In this way, machine failures can be predicted at an early stage, thus avoiding malfunctions, and making maintenance processes efficient.

Traditionally, the raw data is sent to centralized servers where large-scale systems perform analytics on the data gathered from all devices. However, this often leads to high network traffic, latency, and privacy issues. The goal of this work is to analyze the extent to which deep learningbased anomaly detection models can be deployed directly to highly resource-constrained devices (MCUs).

Contact

nikolai.koerber@tum.de

Supervisor:

Nikolai Körber

Improving Accuracy of Binary Neural Networks using Shifting Operations

Keywords:
Binary Neural Networks; Accuracy Improvement

Description

 

Binary neural networks (BNN) are considered to be a promising method to deploy deep neural networks on resource-constrained platforms, e.g., mobile devices. However, they suffer from accuracy degradation compared to the full-precision counterpart model. One of the methods to improve the accuracy of BNN is the expansion of their architectures, since the expanded architecture can provide more computation resources. 

In this master thesis, shifting operations are used to improve the accuracy of binary neural networks. This method can provide additional computation capability for BNNs, so that their architectures might not be expanded to a large degree to compensate accuracy degradation.

 

Contact

If you are interested in this topic for master thesis, please contact: 

Dr.-Ing. Li Zhang (grace-li.zhang@tum.de) with your CV and bachelor and master transcripts.

 

Supervisor:

Li Zhang

Path Delay Prediction with Convolutional Neural Networks

Keywords:
Path Delay Prediction; Convolutional Neural Networks

Description

Due to process variations, the delay of a path is not a deterministic value but a normal distribution. Usually the n×σ points, e.g., 3σ, of the path delay need to be calculated and verified with respect to the timing constraints. These delay points are determined by the path structure, the circuit components on the path and their relative locations. The former defines the types and the sizes of the components, while the latter affects the correlation between their delays. In other words, how a path looks like on the chip after physical design determines the path delay and thus the n×σ points. This graphical appearance of the path can be processed by a convolutional neural network (CNN), which is widely used in computer vision to detect special patterns in images, to produced accurate n×σ points of the path delay. 

 

In this master thesis, a CNN is used to predict the delays of paths after physical design. This method has a great potential in accelerating the delay evaluation, and thus the time-to-market time of IC design.

 

Contact

If you are interested in this topic for master thesis, please contact: 

Dr.-Ing. Li Zhang (grace-li.zhang@tum.de) with your CV and bachelor and master transcripts.

Supervisor:

Li Zhang

Efficient ADC/DAC Designs for RRAM-based Neural Network Accelerators

Keywords:
RRAM; Neural Network Accelerators; ADC/DAC

Description

RRAM-based crossbars shown in Figure 1 are a promising hardware platform to accelerate computations in neural networks. To deploy such crossbars for neural networks in practice, ADCs and DACs are used to convert analog/digital signals into digital/analog signals for further processing. However, existing ADCs and DACs consume a large area and power consumption, which might offset the benefits of analog computing with RRAM crossbars for neural networks. To address this problem, efficient ADC/DAC designs are highly demanded.

 

In this master thesis, a novel ADC/DAC design will be explored, where RRAM cells are exploited to implement the function of ADC/DAC.

Contact

If you are interested in this topic for master thesis, please contact: 

 Amro Eldebiky (amro.eldebiky@tum.de)  with your CV and bachelor and master transcripts.

Supervisor:

Li Zhang

Pruning Neural Networks with Classification Activation Paths

Keywords:
Pruning; Neural Networks, Activation Paths

Description

In recent years, deep neural networks (DNNs) have achieved remarkable breakthroughs. However, there are a huge number of multiply-accumulate operations in DNNs, which restricts their applications in resource-constrained platforms, e.g., mobile phones. To reduce the computation complexity of neural networks, various pruning methods have been developed to reduce the size of models while minimizing loss in accuracy or performance. In the existing neural network pruning methods, weights whose absolute values are small are removed from a trained model. However, these methods do not consider the relationship between different weights.

In this master thesis, a novel pruning method considering classification activation paths will be explored. The basic idea is shown in Figure 1, where a special activation path in the neural network is triggered when a neural network recognizes an image. Such activation paths for various classes will be used to prune neural networks in this master thesis.

Contact

 

If you are interested in this topic for master thesis, please contact: 

Dr.-Ing. Li Zhang (grace-li.zhang@tum.de) with your CV and bachelor and master transcripts.

Supervisor:

Li Zhang

Block-wise Training for Systolic Arrays of Digital Neural Network Accelerators

Keywords:
Neural Network; Systolic Arrays; Block-wise Training

Description

In recent years, deep neural networks (DNNs) have been widely applied in various fields, e.g., image/speech recognition. In DNNs, there are a large number of multiply-accumulate (MAC) operations. To accelerate MAC operations in DNNs, systolic arrays are introduced as an attractive platform due to their high degree of concurrent computation and high data reuse rate. Recently, various state of the art hardware accelerators using systolic arrays or properties of systolic arrays have been proposed. TPU is the most well-known accelerator based on systolic arrays. Systolic arrays have a regular structure where Processing Elements (PEs) are replicated and connected together to process data in a pipelined fashion. Figure 1 shows the structure of the systolic array. However, weights of neural networks after unstructured pruning usually exhibit irregular patterns, as shown in Figure 2. Implementing MAC operations with such irregular weight patterns on systolic arrays with regular designs, might result in an underutilization of hardware resources.

In this master thesis, a block-wise neural network training method will be explored to fully exploit the benefits of systolic arrays. 

 

Contact

If you are interested in this topic for master thesis, please contact: 

Dr.-Ing. Li Zhang (grace-li.zhang@tum.de) with your CV and bachelor and master transcripts.

Supervisor:

Li Zhang

Machine Learning and Neural Networks' Applications in Microfluidics

Short Description:
Neural Network, AI, Machine Learning, Microfluidcs

Description

Machine learning (ML) is taking an important role in our lives these days, which has been widely used in many scenarios. ML methods, including traditional and deep learning algorithms, achieve amazing performance in solving classification, detection, and design space exploration problems.

In recent years, ML for design automation is becoming one of the trending topics and a lot of studies that use ML to improve DA methods have been proposed, which cover almost all the stages in the chip design flow, including design space reduction and exploration, logic synthesis, placement, routing, testing, verification, manufacturing, etc. These ML-based methods have demonstrated impressive improvement compared with traditional methods. In this project, we want to explore and exercise the applications of machine learning and neural networks used for microfluidics design automation.

Prerequisites

  • Knowledge and experience in artificial intelligence and machine learning
  • Good knowledge of Python, Java, or other programming languages and Tensorflow or other ML frameworks or the wiliness to learn them
  • Basic understanding of Generative Adversarial Network or other NN principles
  • Solution-oriented thinking

Contact

If you are interested in this topic, please send your current transcript along with your CV and a short motivation to one of the supervisors' email:

Yushen.Zhang+Project@TUM.de

Supervisor:

Yushen Zhang

Neural Network Evaluation and Enhancement Considering Quantization

Keywords:
Neural Network, Quantization

Description

Neural networks as shown in Figure 1 (see the attached pdf) have successfully been applied to solve complex problems such as speech/image processing. To improve computing accuracy, the depth of neural networks has steadily increased significantly, leading to deep neural networks (DNNs). The increasing complexity has put massive demands on computing power and triggered intensive research on hardware acceleration for neuromorphic computing in recent years. 

The computation function at a neuron in a neural network can be considered as an incompletely specified truth table. The known entries in such a table are determined by the training data. Since training data are usually a small subset of all entries in the truth table, we need to estimate the other entries to realize the logic design with the truth table. The concept of this technique is illustrated in Figure 2 (see the attached pdf), where the neural network is quantized so that the inputs and the outputs of neurons are represented by binary values.

In the quantization, fewer bits reduce resource usage, but the accuracy of the computation may also degrades. In this thesis, a balance between hardware resource and computation accuracy of neural networks will be explored. To compensate the accuracy degradation caused by quantization, the structures of neural networks may also be modified together with quantization to achieve an overall good area efficiency and computation accuracy. The major tasks of this thesis may include:

1. Quantize inputs and outputs of neurons into different number of bits to evaluate the relation between the number of bits and the accuracy of the neural networks.

2. Modification of neural network structures for a tradeoff between accuracy, number of quantization bits and required number of computation operations.

Contact

If you are interested in this topic for master thesis, please contact: 

 Amro Eldebiky (amro.eldebiky@tum.de)  with your CV and transcripts.

 

Supervisor:

Li Zhang

Neural Network Enhancement for Robustness of RRAM-based Design

Keywords:
Neural Network, RRAM, Robustness

Description

RRAM-based crossbars shown in Figure 1 are a promising hardware platform to accelerate computations in neural networks. Before such a crossbar can be used as an accelerator for neural networks, RRAM cells should be programmed to target resistances to represent weights in neural networks. However, this process degrades the valid range of the resistances of RRAM cells from the fresh state, called aging effect. Therefore, after a certain number of programming iterations, the RRAM cells cannot be programmed reliably anymore, affecting the classification accuracy of neural networks negatively. 

 

In neural networks, the weights may have different distributions to achieve the same accuracy. This inherent computation redundancy can be used to reduce the stress on specific and/or overall devices.  Figure 2(a) shows the weight distribution after traditional software training. However, weights in the training can actually be adjusted to avoid those values that cause large currents and thus aging effects. Consequently, the weight distribution after modified training can have a different shape as shown in Figure 2(b). 

 

In this master thesis, an algorithm will be developed to examine the shapes of weight distribution in neural networks and the mapping of weights with respect to aging models. Defects of devices after manufacturing will also be investigated and countered by training and weight mapping. 

Contact

If you are interested in this topic for master thesis, please contact: 

 Amro Eldebiky (amro.eldebiky@tum.de) with your CV and transcripts.

Supervisor:

Li Zhang

Interdisciplinary Projects

Enable Remote Execution of Benchmarks using the MLonMCU TinyML Deployment Tool

Keywords:
MLonMCU, TinyML, Embedded Machine Learning, Benchmark, Python, Remote, Server
Short Description:
MLonMCU is an open source TinyML Benchmarking Flow maintained by our chair. While it was designed for batch processing to exploit parallelism during complex benchmarking sessions, the total execution time of a benchmark is limited by the amount out computational resources available on the local device. In this project you will design and implement a remote execution feature for MLonMCU which allows offloading individual benchmarking runs to a number of remote devices.

Description

The required steps can be described as follows:

  • Get used to the MLonMCU Benchmarking flow
  • Propose a concept for a remote execution of benchmarks
  • Implement remote execution protocol
  • Add more features to improve benchmarking throughput
  • Add detailed documentation

Prerequisites

  • Experience with networking protocols
  • Good Python programming
  • Ideally experience working with UNIX-like operating systems

Supervisor:

Philipp van Kempen

Enable Debugging of RISC-V Vector Instructions using GDB within ETISS simulations

Keywords:
RISC-V, GDB, ETISS, Debug, Vector, RVP
Short Description:
The vector (V) extension for the RISC-V ISA, allows exploiting super-word SIMD instructions to accelerate DSP applications and ML Inference. Currently the upstream debugger for these programs is lacking some essential features to debug the vector instructions and the contents vector register space in an ETISS Simulation environment.

Description

The required steps can be summarized as follows:

  • Patch RISC-V GDB to decode vector instructions properly
  • Extend RISC-V GDB suite to allow printing of the values for the available vector registers
  • Update ETISS GDBServer implementation to expose all vector registers to debugger clients.

Prerequisites

  • Instruction Set Architectures
  • Experience with ETISS Simulator
  • Debugging Embedded Software
  • Experience working with a complex C/C++ codebase

Supervisor:

Philipp van Kempen

Online Microfluidics Programming Platform

Keywords:
Microfluidics, Lab-On-Chip, Programming
Short Description:
We want to introduce an interactive but intuitive programming platform for microfluidic researchers that do not require any pre-experience with programming.

Description

Microfluidic Large Scale Integration (mLSI) refers to the development of microfluidic chips with thousands of integrated micromechanical valves and control components. This technology is used in many areas of biology and chemistry and is a candidate for replacing today's conventional automation paradigm, which consists of Robots for handling liquids.

 

To enable automated control of mLSI, programming sequence for valve control and fluid inputs is essential. Although, not every researcher, especially biologists or chemists, has programming skills. We want to introduce an interactive but intuitive programming platform for microfluidic researchers that do not require any pre-experience with programming to overcome this problem.

 

This platform provides a visual programming language that allows users to define their needs by dragging and dropping the command blocks into a canvas. A flow simulation will show up on the side when users click on the run. 

Prerequisites

  • Knowledge and experience in web design and web development
  • Good knowledge of HTML5, CSS, JavaScript and PHP (or Java Spring Boot) or the wiliness to learn them
  • Basic knowledge of SQL, jQuery and Vue.js (or other frontend framework) or the wiliness to learn them
  • Solution-oriented thinking

 

Contact

If you are interested in this topic, please send your current transcript along with your CV and a short motivation to one of the supervisors' email:

Yushen.Zhang+Project@TUM.de

Supervisor:

Yushen Zhang

Machine Learning and Neural Networks' Applications in Microfluidics

Short Description:
Neural Network, AI, Machine Learning, Microfluidcs

Description

Machine learning (ML) is taking an important role in our lives these days, which has been widely used in many scenarios. ML methods, including traditional and deep learning algorithms, achieve amazing performance in solving classification, detection, and design space exploration problems.

In recent years, ML for design automation is becoming one of the trending topics and a lot of studies that use ML to improve DA methods have been proposed, which cover almost all the stages in the chip design flow, including design space reduction and exploration, logic synthesis, placement, routing, testing, verification, manufacturing, etc. These ML-based methods have demonstrated impressive improvement compared with traditional methods. In this project, we want to explore and exercise the applications of machine learning and neural networks used for microfluidics design automation.

Prerequisites

  • Knowledge and experience in artificial intelligence and machine learning
  • Good knowledge of Python, Java, or other programming languages and Tensorflow or other ML frameworks or the wiliness to learn them
  • Basic understanding of Generative Adversarial Network or other NN principles
  • Solution-oriented thinking

Contact

If you are interested in this topic, please send your current transcript along with your CV and a short motivation to one of the supervisors' email:

Yushen.Zhang+Project@TUM.de

Supervisor:

Yushen Zhang

Research Internships (Forschungspraxis)

Dataset Generation for Graph Attention Network-based Power Estimation

Description

In System on Chip (SoC) design, power consumption gets increasingly important (e.g. due to increasing complexity of the devices and contrary, due to the growing number of mobile applications). Although precise gate-level simulation methods exist, they are often not feasible for larger designs. Therefore, less accurate, but faster methods have been developed [1]. For dynamic power dissipation, the switching activity of a design is crucial (beside technological parameters). Here, already approaches for its estimation based on Machine Learning, namely Graph Neural Networks (GNN), have been developed [2]. 

But, existing approaches require detailed information about the structure of a circuit (e.g. the gate level netlist) for exact power estimation. This information may not be always available (e.g. in early design stages or in black-box IP blocks). Therefore, approaches to achieve a exact power estimation with limited knowledge would be appreciated. In previous work, a framework for power estimation based on Graph Attention Neural Networks (GAT) has been developed to obtain power estimations based on only the primary input and output signals of a design and its relationships, modelled as graphs.

In this project, a dataset with multiple reference designs (e.g. benchmark circuits or open-source cores) should be generated to enable further training of the GAT-based power estimation framework. This includes the selection of appropriate reference designs, their synthesis and physical design in respective tools and the extraction power wavefroms from gate level simulation. Furthermore, a framework for automatic dataset generation may be developed.


[1] NAJM, Farid N.; XAKELLIS, Michael G. Statistical Estimation of the, Switching Activity in VLSI Circuits. VLSI Design, 1998, 7. Jg., Nr. 3, S. 243-254.

[2] ZHANG, Yanqing; REN, Haoxing; KHAILANY, Brucek. GRANNITE: Graph neural network inference for transferable power estimation. In: 2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020. S. 1-6.

 

Prerequisites

  • Experience in Python programming would be beneficial
  • Knowledge in HDLs and CMOS power consumption
  • Interest in the ASIC Development Flow and Machine Learning in EDA
  • Ability to work independently

 

Contact

If you are interested in this topic, please feel free to contact me at:

philipp.fengler@tum.de

Supervisor:

Philipp Fengler

Enable Remote Execution of Benchmarks using the MLonMCU TinyML Deployment Tool

Keywords:
MLonMCU, TinyML, Embedded Machine Learning, Benchmark, Python, Remote, Server
Short Description:
MLonMCU is an open source TinyML Benchmarking Flow maintained by our chair. While it was designed for batch processing to exploit parallelism during complex benchmarking sessions, the total execution time of a benchmark is limited by the amount out computational resources available on the local device. In this project you will design and implement a remote execution feature for MLonMCU which allows offloading individual benchmarking runs to a number of remote devices.

Description

The required steps can be described as follows:

  • Get used to the MLonMCU Benchmarking flow
  • Propose a concept for a remote execution of benchmarks
  • Implement remote execution protocol
  • Add more features to improve benchmarking throughput
  • Add detailed documentation

Prerequisites

  • Experience with networking protocols
  • Good Python programming
  • Ideally experience working with UNIX-like operating systems

Supervisor:

Philipp van Kempen

Automatic Generation of RISC-V Special Instructions in SW Toolchains

Short Description:
In this thesis, a method and implementation should be developed in order to automatically generate patches for the LLVM and GCC toochain from a formal definition of a special instruction.

Description

RISC-V is a new, open instruction set architecture (ISA) that, as a core feature, can be extended with special instructions to customize embedded processors to special applications such as frm the control and machine learning domain.

We already developed a customizable simulator named ETISS, that can quickly evaluate the benefit of special instructions for a given application. Next to the core, also the compiler and assembler support for creating a binary from embedded C code is required by designers to exploit performance benefits of special instructions.

In this thesis, a method and implementation should be developed in order to automatically generate patches for the LLVM and GCC toochain from a formal definition of a special instruction. There are various levels of special instruction support possible in the toolchain, that should be explored within this thesis.

Supervisor:

Internships

Online Microfluidics Programming Platform

Keywords:
Microfluidics, Lab-On-Chip, Programming
Short Description:
We want to introduce an interactive but intuitive programming platform for microfluidic researchers that do not require any pre-experience with programming.

Description

Microfluidic Large Scale Integration (mLSI) refers to the development of microfluidic chips with thousands of integrated micromechanical valves and control components. This technology is used in many areas of biology and chemistry and is a candidate for replacing today's conventional automation paradigm, which consists of Robots for handling liquids.

 

To enable automated control of mLSI, programming sequence for valve control and fluid inputs is essential. Although, not every researcher, especially biologists or chemists, has programming skills. We want to introduce an interactive but intuitive programming platform for microfluidic researchers that do not require any pre-experience with programming to overcome this problem.

 

This platform provides a visual programming language that allows users to define their needs by dragging and dropping the command blocks into a canvas. A flow simulation will show up on the side when users click on the run. 

Prerequisites

  • Knowledge and experience in web design and web development
  • Good knowledge of HTML5, CSS, JavaScript and PHP (or Java Spring Boot) or the wiliness to learn them
  • Basic knowledge of SQL, jQuery and Vue.js (or other frontend framework) or the wiliness to learn them
  • Solution-oriented thinking

 

Contact

If you are interested in this topic, please send your current transcript along with your CV and a short motivation to one of the supervisors' email:

Yushen.Zhang+Project@TUM.de

Supervisor:

Yushen Zhang

Student Assistant Jobs

Enable Debugging of RISC-V Vector Instructions using GDB within ETISS simulations

Keywords:
RISC-V, GDB, ETISS, Debug, Vector, RVP
Short Description:
The vector (V) extension for the RISC-V ISA, allows exploiting super-word SIMD instructions to accelerate DSP applications and ML Inference. Currently the upstream debugger for these programs is lacking some essential features to debug the vector instructions and the contents vector register space in an ETISS Simulation environment.

Description

The required steps can be summarized as follows:

  • Patch RISC-V GDB to decode vector instructions properly
  • Extend RISC-V GDB suite to allow printing of the values for the available vector registers
  • Update ETISS GDBServer implementation to expose all vector registers to debugger clients.

Prerequisites

  • Instruction Set Architectures
  • Experience with ETISS Simulator
  • Debugging Embedded Software
  • Experience working with a complex C/C++ codebase

Supervisor:

Philipp van Kempen