Here you can find all available student positions of our chair. We offer master theses, bachelor theses, research internships, industry internships and interdisciplinary projects. If you cannot find a suitable offering, please contact one of our research members. To find more information about the research topics of our chair you can visit Research. Furthermore, we offer seminar topics.

 

Bachelor's Theses

AST Simplification and Optimization for M2-ISA-R Models

Description

M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.

The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.

Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.

Prerequisites

  • Interest in learning about symbolic evaluation and simplification
  • Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
  • Very good knowledge of Python
  • Some experience with parser generators, ideally ANTLR4

Contact

karsten.emrich@tum.de

Supervisor:

Karsten Emrich

Master's Theses

Integration of Deep Learning Backends Using Collage

Short Description:
The thesis will contribute to the research on Collage for integration of Deep Learning (DL) backends and provide insights into the challenges in this field.

Description

The thesis will contribute to the research on Collage for integration of Deep Learning (DL) backends and provide insights into the challenges in this field. The strong demand for efficient and performant deployment of DL applications prompts the rapid development of a rich DL ecosystem. To keep up with this fast advancement, it is crucial for modern DL frameworks to efficiently integrate a variety of optimized tensor algebra libraries and runtimes as their backends and generate the fastest possible executable using these backends. However, current DL frameworks require significant manual effort and expertise to integrate every new backend while failing to unleash its full potential. Given the fast-evolving nature of the DL ecosystem, this manual approach often slows down continuous innovations across different layers; it prevents hardware vendors from the fast deployment of their cutting-edge libraries, DL framework developers must repeatedly adjust their hand-coded rules to accommodate new versions of libraries, and machine learning practitioners need to wait for the integration of new technologies and often encounter unsatisfactory performance. Collage is a DL framework that offers seamless integration of DL backends. Collage provides an expressive backend registration interface that allows users to precisely specify the capability of various backends. By leveraging the specifications of available backends, Collage automatically searches for an optimized backend placement strategy for a given workload and execution environment.

Your work:

  1. Conduct a comprehensive literature review on Collage and similar frameworks
  2. Conduct an experiment on Collage including a heterogenous system including UMA-integrated backends in TVM 

Prerequisites

  • Fundamental understanding of neural networks and embedded systems
  • Basic understanding of TVM compiler
  • Experience in programming C\C++ and Python
  • Self-motivation and ability to work independently 

Contact

If you are interested in this topic, please contact me at samira.ahmadifarsani@tum.de.

Supervisor:

Samira Ahmadifarsani

Memory-Oriented Approaches for Deployment of DNNs on Low-Cost Edge Heterogeneous Systems

Short Description:
The thesis will contribute to the research on memory-centric approaches for the deployment of DNN models on resource-constraint heterogeneous systems and provide insights into the existing challenges in this field.

Description

The thesis will contribute to the research on memory-centric approaches for the deployment of DNN models on resource-constraint heterogeneous systems and provide insights into the existing challenges in this field. In recent years, the rapid growth of Artificial Intelligence (AI) and the explosion of hardware devices with AI-specific features have led to a rising demand for tools and frameworks capable of translating Deep Learning models from high-level languages like Python into lower-level code optimized for a particular hardware target, often in C. This thesis focuses on edge heterogeneous systems with limited computational capabilities and low memory and prioritizes energy efficiency. The proliferation of diverse hardware platforms and programming ecosystems makes porting AI models to every device a non-trivial task. An ideal solution would be a universal tool that can translate high-level model representations, e.g., in Python, into low-level code while accommodating various hardware constraints, programming languages, and interfaces. Unfortunately, achieving this goal without compromising performance is still a challenge. For example, the TVM compiler stack is a popular open-source toolchain for deploying networks on many devices, including CPUs, GPUs, or ARM and RISC-V-based Microcontrollers (MCUs) but falls short when generating code for heterogeneous Systems-on-Chip (SoCs) containing different accelerators. Recent efforts have focused on integrating TVM with memory-oriented deployment frameworks like DORY [1] and ZigZag [2], aiming to address these challenges.

[1] Van Delm, et al. "HTVM: Efficient neural network deployment on heterogeneous TinyML platforms." In 2023 60th ACM/IEEE Design Automation Conference (DAC), pp. 1-6. IEEE, 2023.

[2] Hamdi, Mohamed Amine. "Integrating Design Space Exploration in Modern Compilation Toolchains for Deep Learning." PhD diss., Politecnico di Torino, 2023.

Your work:
1. Conduct a comprehensive literature review of existing works.
2. Compare the references to identify gaps and unresolved challenges. 3. Investigate the integration flow of references 1 and 2 in TVM.
4. Work on integrating the approaches outlined in references 1 and 2 using the UMA framework within TVM.  

Prerequisites

Requirements:

  • Fundamental understanding of neural networks and embedded systems
  • Basic understanding of TVM compiler
  • Experience in programming C\C++ and Python
  • Self-motivation and ability to work independently 

Contact

If you are interested in this topic, please contact me at samira.ahmadifarsani@tum.de.

Supervisor:

Samira Ahmadifarsani

PhD Project in Hamburg (NXP Semiconductors): Variation-aware Model-based Design of AMS/RF Systems

Description

see attached pdf

Contact

carna.zivkovic@nxp.com

Supervisor:

Susanne Werner - Carna Zivkovic (NXP Semiconductors Hamburg)

AST Simplification and Optimization for M2-ISA-R Models

Description

M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.

The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.

Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.

Prerequisites

  • Interest in learning about symbolic evaluation and simplification
  • Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
  • Very good knowledge of Python
  • Some experience with parser generators, ideally ANTLR4

Contact

karsten.emrich@tum.de

Supervisor:

Karsten Emrich

Automatic Categorization and Filtering of Research Data via Machine Learning Methods

Description

 

Analog circuit design, to this day, highly depends on expert knowledge. Similarly, efforts in analog design automation include the construction of databases of various sorts, such as analog building blocks, or entire netlists. Much of the necessary knowledge for cunstring such databases is either hidden within the analog designer’s mind, or by extension in published articles. With the recent success in language processing, an opportunity for automatic sighting and analysis of data arises. In this work, experiments with language models will be conducted, with the goal of building a database of articles treating a specific subject in analog design.

 

 

Supervisor:

Markus Leibl

Performance Evaluation of a RISC-V CPU

Keywords:
RISC-V, ISS, RTL, ESL, VP, ETISS, Performance, Embedded Systems

Description

This project is proposed and conducted in cooperation with MINRES Technologies.

RISC-V is an open-source instruction set architecture (ISA), which has recently gained a lot of interest in both academia and commercial contexts. One of the key features of the RISC-V architecture is its flexibility, which, for instance, allows chip designers to add custom instructions to support their specific use cases. Further, due to its open-source character, designers are free to implement their own, customized RISC-V microarchitecture.

To fully utilize the flexibility of RISC-V, different design choices should be explored, in order to find the best suited solution. Such a so-called design space exploration (DSE) typically relies on abstract models of the actual hardware, which can be quickly modified to cover different design choices. As high execution speed is frequently of major importance for a processor, accuratly depicting the processor's performance is one of the key requirements for this type of models.

During this project, abstract performance models shall be generated for an existing RISC-V CPU, developted by MINRES Technologies, in order to evaluate its performance. To achieve this, the student will:

  1. Integrate a tool-chain for performance modelling, developted at TUM, into the simulation environment of MINRES, in order to establish a common workflow.
  2. Use the established workflow to generate abstract performance models of an existing RISC-V CPU, developted by MINRES.
  3. Evaluate the accuracy of the generated models, by comparing their performance estimates with the actual performance of the CPU.

Prerequisites

 This project requires

  • A fundamental understanding of the functionality of processors and basic microarchitectural concepts
  • Solid experience in object-oriented programming.
  • Experience in programming with C++ and Python3 are a major benefit

Contact

If you are interested in the project or have further questions, please do not hesitate to contact me under conrad.foik@tum.de

Supervisor:

Conrad Foik - Rocco Jonack (MINRES Technologies)

Interdisciplinary Projects

AST Simplification and Optimization for M2-ISA-R Models

Description

M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.

The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.

Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.

Prerequisites

  • Interest in learning about symbolic evaluation and simplification
  • Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
  • Very good knowledge of Python
  • Some experience with parser generators, ideally ANTLR4

Contact

karsten.emrich@tum.de

Supervisor:

Karsten Emrich

Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge

Keywords:
Microsystem, MEMS, Innovation, Creativity
Short Description:
This is a dynamic and hands-on internship designed to empower students to harness their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming an innovative entrepreneur in the realm of sensor and microsystem applications. At the end of this contest, you will be credited with the credits for FP/IP/IDP.

Description

Welcome to "Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge," a dynamic and hands-on internship designed to empower students in harnessing their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming innovative entrepreneurs in the realm of sensor and microsystem applications.

 

Overview:

In this practical internship, students will delve into the world of microsystems, exploring their components, functionalities, and potential applications. The focus will be on fostering creativity and teamwork as students work collaboratively to conceive, design, and prototype innovative solutions using sensors and microsystems.

 

Key Features:

Creative Exploration: Unlike traditional courses and internships, this one offers the freedom to choose and define your own technical challenge. Students will be encouraged to think outside the box, identify real-world problems, and propose solutions that leverage microsystems to enhance human-technology interactions.

 

Hands-On Prototyping: The heart of the internship lies in turning ideas into reality. Students will actively engage in the prototyping process, developing functional prototypes of their innovative concepts. Emphasis will be placed on understanding the practical aspects of sensor integration, actuation, and control electronics.

 

COSIMA Contest Preparation: The internship will align with the COSIMA contest requirements, preparing students to present their prototypes on the competition day. Guidance will be provided on creating impactful presentations that showcase the ingenuity and practicality of their solutions.

 

Go International: The winners of COSIMA will qualify to take part in the international iCAN competition. Guidance and preparation for the iCAN will be provided.

 

Entrepreneurial Mindset: Drawing inspiration from successful startups that emerged from COSIMA, the internship will instill an entrepreneurial mindset. Students will learn about the essentials of founding a startup, from business planning to pitching their ideas.

 

Us in the past:

Das war COSIMA 2023 (cosima-mems.de)

iCAN Wettbewerb 2023 (cosima-mems.de)

Sieger 2022 (cosima-mems.de)

Prerequisites

Intermediate German and English language proficiency is required.

Contact

Supervisor:

Yushen Zhang

Research Internships (Forschungspraxis)

Implementation of Optimization Models for Optical Networks-on-Chip

Description

Optical networks-on-chip (ONoC) has emerged, becoming a promising next-generation communication platform. As a type of ONoC, wavelength-routed optical networks-on-chip (WRONoC) exhibit ultra-high bandwidth and ultra-low latency in data communications. Emerging optimization models combine automatic topology customization and optimization methods with ILP and sweeping techniques to overcome runtime issues and provide multiple topology variations with different port orders for the physical layout.

The objectives of this research internship are:

  • implement the optimization models for WRONoC topology customization design.
  • Package code into Docker containers.

Prerequisites

  • Programming skills
  • Knowledge of integer-linear programming models and algorithm design
  • Experience with Gurobi Solver is preferred

Contact

If you are interested in this topic, please send your resume, transcript, and a brief motivation to: 

liaoyuan.cheng@tum.de  

Supervisor:

Liaoyuan Cheng

AST Simplification and Optimization for M2-ISA-R Models

Description

M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.

The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.

Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.

Prerequisites

  • Interest in learning about symbolic evaluation and simplification
  • Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
  • Very good knowledge of Python
  • Some experience with parser generators, ideally ANTLR4

Contact

karsten.emrich@tum.de

Supervisor:

Karsten Emrich

Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge

Keywords:
Microsystem, MEMS, Innovation, Creativity
Short Description:
This is a dynamic and hands-on internship designed to empower students to harness their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming an innovative entrepreneur in the realm of sensor and microsystem applications. At the end of this contest, you will be credited with the credits for FP/IP/IDP.

Description

Welcome to "Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge," a dynamic and hands-on internship designed to empower students in harnessing their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming innovative entrepreneurs in the realm of sensor and microsystem applications.

 

Overview:

In this practical internship, students will delve into the world of microsystems, exploring their components, functionalities, and potential applications. The focus will be on fostering creativity and teamwork as students work collaboratively to conceive, design, and prototype innovative solutions using sensors and microsystems.

 

Key Features:

Creative Exploration: Unlike traditional courses and internships, this one offers the freedom to choose and define your own technical challenge. Students will be encouraged to think outside the box, identify real-world problems, and propose solutions that leverage microsystems to enhance human-technology interactions.

 

Hands-On Prototyping: The heart of the internship lies in turning ideas into reality. Students will actively engage in the prototyping process, developing functional prototypes of their innovative concepts. Emphasis will be placed on understanding the practical aspects of sensor integration, actuation, and control electronics.

 

COSIMA Contest Preparation: The internship will align with the COSIMA contest requirements, preparing students to present their prototypes on the competition day. Guidance will be provided on creating impactful presentations that showcase the ingenuity and practicality of their solutions.

 

Go International: The winners of COSIMA will qualify to take part in the international iCAN competition. Guidance and preparation for the iCAN will be provided.

 

Entrepreneurial Mindset: Drawing inspiration from successful startups that emerged from COSIMA, the internship will instill an entrepreneurial mindset. Students will learn about the essentials of founding a startup, from business planning to pitching their ideas.

 

Us in the past:

Das war COSIMA 2023 (cosima-mems.de)

iCAN Wettbewerb 2023 (cosima-mems.de)

Sieger 2022 (cosima-mems.de)

Prerequisites

Intermediate German and English language proficiency is required.

Contact

Supervisor:

Yushen Zhang

Performance Evaluation of a RISC-V CPU

Keywords:
RISC-V, ISS, RTL, ESL, VP, ETISS, Performance, Embedded Systems

Description

This project is proposed and conducted in cooperation with MINRES Technologies.

RISC-V is an open-source instruction set architecture (ISA), which has recently gained a lot of interest in both academia and commercial contexts. One of the key features of the RISC-V architecture is its flexibility, which, for instance, allows chip designers to add custom instructions to support their specific use cases. Further, due to its open-source character, designers are free to implement their own, customized RISC-V microarchitecture.

To fully utilize the flexibility of RISC-V, different design choices should be explored, in order to find the best suited solution. Such a so-called design space exploration (DSE) typically relies on abstract models of the actual hardware, which can be quickly modified to cover different design choices. As high execution speed is frequently of major importance for a processor, accuratly depicting the processor's performance is one of the key requirements for this type of models.

During this project, abstract performance models shall be generated for an existing RISC-V CPU, developted by MINRES Technologies, in order to evaluate its performance. To achieve this, the student will:

  1. Integrate a tool-chain for performance modelling, developted at TUM, into the simulation environment of MINRES, in order to establish a common workflow.
  2. Use the established workflow to generate abstract performance models of an existing RISC-V CPU, developted by MINRES.
  3. Evaluate the accuracy of the generated models, by comparing their performance estimates with the actual performance of the CPU.

Prerequisites

 This project requires

  • A fundamental understanding of the functionality of processors and basic microarchitectural concepts
  • Solid experience in object-oriented programming.
  • Experience in programming with C++ and Python3 are a major benefit

Contact

If you are interested in the project or have further questions, please do not hesitate to contact me under conrad.foik@tum.de

Supervisor:

Conrad Foik - Rocco Jonack (MINRES Technologies)

Internships

Implementation of Optimization Models for Optical Networks-on-Chip

Description

Optical networks-on-chip (ONoC) has emerged, becoming a promising next-generation communication platform. As a type of ONoC, wavelength-routed optical networks-on-chip (WRONoC) exhibit ultra-high bandwidth and ultra-low latency in data communications. Emerging optimization models combine automatic topology customization and optimization methods with ILP and sweeping techniques to overcome runtime issues and provide multiple topology variations with different port orders for the physical layout.

The objectives of this research internship are:

  • implement the optimization models for WRONoC topology customization design.
  • Package code into Docker containers.

Prerequisites

  • Programming skills
  • Knowledge of integer-linear programming models and algorithm design
  • Experience with Gurobi Solver is preferred

Contact

If you are interested in this topic, please send your resume, transcript, and a brief motivation to: 

liaoyuan.cheng@tum.de  

Supervisor:

Liaoyuan Cheng

AST Simplification and Optimization for M2-ISA-R Models

Description

M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.

The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.

Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.

Prerequisites

  • Interest in learning about symbolic evaluation and simplification
  • Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
  • Very good knowledge of Python
  • Some experience with parser generators, ideally ANTLR4

Contact

karsten.emrich@tum.de

Supervisor:

Karsten Emrich

Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge

Keywords:
Microsystem, MEMS, Innovation, Creativity
Short Description:
This is a dynamic and hands-on internship designed to empower students to harness their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming an innovative entrepreneur in the realm of sensor and microsystem applications. At the end of this contest, you will be credited with the credits for FP/IP/IDP.

Description

Welcome to "Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge," a dynamic and hands-on internship designed to empower students in harnessing their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming innovative entrepreneurs in the realm of sensor and microsystem applications.

 

Overview:

In this practical internship, students will delve into the world of microsystems, exploring their components, functionalities, and potential applications. The focus will be on fostering creativity and teamwork as students work collaboratively to conceive, design, and prototype innovative solutions using sensors and microsystems.

 

Key Features:

Creative Exploration: Unlike traditional courses and internships, this one offers the freedom to choose and define your own technical challenge. Students will be encouraged to think outside the box, identify real-world problems, and propose solutions that leverage microsystems to enhance human-technology interactions.

 

Hands-On Prototyping: The heart of the internship lies in turning ideas into reality. Students will actively engage in the prototyping process, developing functional prototypes of their innovative concepts. Emphasis will be placed on understanding the practical aspects of sensor integration, actuation, and control electronics.

 

COSIMA Contest Preparation: The internship will align with the COSIMA contest requirements, preparing students to present their prototypes on the competition day. Guidance will be provided on creating impactful presentations that showcase the ingenuity and practicality of their solutions.

 

Go International: The winners of COSIMA will qualify to take part in the international iCAN competition. Guidance and preparation for the iCAN will be provided.

 

Entrepreneurial Mindset: Drawing inspiration from successful startups that emerged from COSIMA, the internship will instill an entrepreneurial mindset. Students will learn about the essentials of founding a startup, from business planning to pitching their ideas.

 

Us in the past:

Das war COSIMA 2023 (cosima-mems.de)

iCAN Wettbewerb 2023 (cosima-mems.de)

Sieger 2022 (cosima-mems.de)

Prerequisites

Intermediate German and English language proficiency is required.

Contact

Supervisor:

Yushen Zhang

Student Assistant Jobs

Studentische Hilfskraft FPGA-Synthese und Programmierung

Description

siehe angehängtes pdf-File

Contact

Supervisor:

Ulf Schlichtmann - Thomas Becker (Lehrstuhl für Brau- und Getränketechnologie)

AST Simplification and Optimization for M2-ISA-R Models

Description

M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.

The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.

Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.

Prerequisites

  • Interest in learning about symbolic evaluation and simplification
  • Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
  • Very good knowledge of Python
  • Some experience with parser generators, ideally ANTLR4

Contact

karsten.emrich@tum.de

Supervisor:

Karsten Emrich