Motivation

RISC-V is a modular and open instruction set architecture (ISA) that allows for seamless integration of custom instructions to tailor processors for specific application domains such as signal processing, control systems, and machine learning. Designing efficient custom instructions, however, requires careful co-optimization of hardware and software components to achieve meaningful performance and area benefits.

State of the Art

Recent advancements in the RISC-V ecosystem have significantly simplified the implementation of custom instructions. Standardized extension interfaces such as SCAIE-V[1] and CV-X-IF[2] eliminate the need for ad hoc integration efforts, improving portability and reducing the amount of RTL modification required when targeting different cores. On the software side, retargetable compiler frameworks like Seal5[3] streamline the integration of instruction set extensions into existing compiler flows, making the exploitation of custom instructions more accessible.

At our chair, the GenIE[4] framework has been developed to automate the design of custom RISC-V instructions, covering ISA specification, RTL generation, core integration, and evaluation of hardware overheads. However, the current flow relies on proprietary tools and supports only a single HLS backend (Longnail[5]) and a fixed extension interface (SCAIE-V[1]). This thesis aims to generalize the framework to support multiple HLS tools and extension interfaces, increasing flexibility and reusability across different hardware and software environments.

Task Description

This thesis explores a high-level synthesis (HLS)-based approach to evaluate and optimize the hardware implementation of custom RISC-V instructions. Using tools such as CoreDSL[6], CorePerfDSL[7], ETISS[8] and the PandA Bambu HLS[9] framework, the goal is to establish an end-to-end flow from ISA-level specification to hardware generation and performance estimation. The work will cover manual and automated translation from ISA descriptions to HLS input, optimization of hardware via scheduling and design space exploration, and integration with extensible RISC-V cores using interfaces like SCAIE-V and CV-X-IF. Evaluation includes comparing different HLS tools, assessing performance and area trade-offs, and validating estimator accuracy against synthesis results. The outcome will be a flexible and extensible framework to support research and development in custom RISC-V instruction design using HLS techniques.

Precise power estimates enable more efficient designs and give directions for energy saving. This enhances battery cycles and limits the need for cooling setups. However, currently power estimates are mostly based on date from late stages in the design process. However, the largest knobs for improvements in the system architecture exist in early design stages on the high level design, which can be modeled for example with SystemC.

This area is tackled by this year's challenge of the DVCon in Munich in October 2025:

Prerequisites