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VHDL System Design Laboratory

Lecturer (assistant)
Yushen Zhang
Alexandre Truppel
Johannes Geier
Philipp Fengler
Ulf Schlichtmann
Number 0000001853
Type practical training
Duration 4 SWS
Term Wintersemester 2024/25
Language of instruction English
Position within curricula See TUMonline

Admission information

See TUMonline
Note: Attendance of the FIRST LECTURE is MANDATORY for all students, and any student who misses the first lecture will be removed from the course. Please note that only students who have received the status "Confirmed place/Fixplatz" have a spot in this course. All students with "Requirements met/Voraussetzungen erfüllt" are on the waiting list. If you are on the waiting list and still wish to attend the course, we strongly recommend that you join the first lecture, as you still have a chance to get into the course. Please note that any student who does not show up for the first lecture will be removed and will be replaced by students on the waiting list who attend the first lecture.

Objectives

At the end of the module students will be able to analyze and evaluate System-on-Chip and embedded system concepts. They are capable of designing and creating SoCs and embedded systems with their complex system components.

Description

Concept of System-on-Chip (SoC); build an example of an embedded system with microcontroller, bus and peripherals; first implement an encryption algorithm using a standard hardware description language; then wrap the security module as a peripheral attached to bus; design an interface between peripheral and bus; apply an FPGA design flow for embedded systems, and embedded software for testing the encryption algorithm.

Prerequisites

Fundamentals of digital logic design; Fundamentals of programming

Teaching and learning methods

In addition to the individual methods of the students consolidated knowledge is acquired by providing subtasks of increasing complexity and difficulty in the laboratory notes.

Teaching method:
Students are free to work on their own, according to their own schedule, on the laboratory tasks. Students can work on the laboratory either in institute rooms, or at home. An adviser is available who will support them in case of significant difficulties.

The following kinds of media are used:
* Introductory lectures
* Lecture slides available
* Laboratory notes with detailed descriptions of tasks and tool environments
* Individual discussions with advisor

Examination

Examination with the following elements:
* Written examination 60 min. (40%)
* project (60%)

Knowledge-based teaching targets are examined with a written examination.
Capabilities of designing a System on Chip are examined by a project consisting of design tasks on the System components and the system composition using a hardware description language. The examination is in form of software code and of a documentation of the design.

Recommended literature

The following literature is recommended:
* ANSI, IEEE Standards Board, IEEE Standard VHDL Language Reference Manual: IEEE Std 1076-1993 , New York, 1988, ISBN 1559373768
* Peter J. Ashenden, Designer’s Guide to Vhdl, Morgan Kaufmann Publishers, 1995, ISBN 1558602704
* More literature listed in laboratory notes

Links

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All courses

Bachelorbereich: BSc-EI, BSES, BSEDE

WSSSDiskrete Mathematik für Ingenieure (BSEI, EI00460) Discrete Mathematics for Engineers (BSEDE ) (Schlichtmann) (Januar)
WSSSEntwurf digitaler Systeme mit VHDL u. System C (BSEI, EI0690) (Ecker)
 SSEntwurfsverfahren für integrierte Schaltungen (BSES, EI43811) (Schlichtmann)
 SSSchaltungssimulation (BSEI, EI06691) (Gräb/Schlichtmann)

 

Masterbereich: MSc-EI, MSCE, ICD

 SSAdvanced Topics in Communication Electronics (MSCE, MSEI, EI79002) 
 SSElectronic Design Automation (MSCE, MSEI, EI70610) (Schlichtmann, Tseng) 
WS Design Methodology and Automation (ICD) (Schlichtmann) (Nov) 
WSSSEmbedded System Design for Machine Learning (MSCE, MSEI, EI71040) (Ecker) 
 SSSimulation and Optimization of Analog Circuits (ICD) (Gräb) (Mai) 
 SSMixed Integer Programming and Graph Algorithms in Engineering Problems (MSCE, MSEI, EI71059) (Tseng) 
WSSSNumerische Methoden der Elektrotechnik (MSEI, EI70440) (Schlichtmann oder Truppel) 

WS

WS

SS

Seminar VLSI-Entwurfsverfahren (MSEI, EI7750) (Schlichtmann)

Seminar on Topics in Electronic Design Automation (MSCE, EI77502) (Schlichtmann)

 
WSSSSynthesis of Digital Systems (MSCE, MSEI, EI70640) (Geier) 
WS Testing Digital Circuits (MSCE, MSEI, EI50141) (Otterstedt) 
WSSSVHDL System Design Laboratory (MSCE, MSEI, EI7403) (Schlichtmann) 

BSES: Bachelor of Science Engineering Science (TUM-ED)

BSEDE: Bachelor of Science in Electronics and Data Engineering (TUM-Asia)

ICD: Master of Science in Integrated Circuit Design (TUM-Asia)

MSCE: Master of Science in Communications Engineering (TUM)

MSEI: Master of Science in Elektrotechnik und Informationstechnik

BSEI: Bachelor of Science in Elektrotechnik und Informationstechnik

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