M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.

The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.

Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.

• Interest in learning about symbolic evaluation and simplification
• Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
• Very good knowledge of Python
• Some experience with parser generators, ideally ANTLR4

Steps:

1. Literature research
2. Setup toolset (CoreDSL2 + M2-ISA-R + ETISS + LLVM + MLonMCU + TVM + muRISCV-NN)
3. Implement (or generate) RISC-V (Embedded) Vector Instructions in CoreDSL comparing 2 different Approaches
   1. (A) Using external softvector library implemented in C++
   2. (B) By writing all instruction behavior in CoreDSL syntax
4. Generate ETISS Architectures to test and verify the vector instructions
5. Run Benchmarks of vectorized programs on ETISS with MLonMCU tool
6. Compare Approach (A) & (B) in terms of
   1. LoCs (CoreDSL & C++)
   2. Simulated MIPS
   3. Generation Runtime
   4. Difficulty
   5. …
7. Optional: Integration of (Embedded) Vector Extension in TVM
   1. Using fixed/scalable vectors
   2. Autotuning with MetaScheduler
   3. Implement RVV-specific tensor instrinsics

• https://github.com/riscv/riscv-v-spec
• https://github.com/tum-ei-eda/etiss
• https://ieeexplore.ieee.org/document/8547814
• https://riscv-europe.org/summit/2023/media/proceedings/posters/2023-06-07-Karsten-EMRICH-abstract.pdf
• https://ieeexplore.ieee.org/abstract/document/10305465
• https://ieeexplore.ieee.org/abstract/document/9774593/
• https://github.com/Minres/CoreDSL/wiki/CoreDSL-2-programmer's-manual
• https://ieeexplore.ieee.org/abstract/document/9774593
• https://ieeexplore.ieee.org/document/9424273

• Experience with Low-Level Embedded Systems Programming (Assembly)
• Strong background in C++ and Python programming
• Ideally some knownledge about the RISC-V ISA
• Basic understanding of HW acceleration concepts such as SIMD (single-instruction multiple-data)
• Experience with Git and Debian/Ubuntu based operating systems (or similar)

M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.

The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.

Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.

• Interest in learning about symbolic evaluation and simplification
• Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
• Very good knowledge of Python
• Some experience with parser generators, ideally ANTLR4

Analog circuit design, to this day, highly depends on expert knowledge. Similarly, efforts in analog design automation include the construction of databases of various sorts, such as analog building blocks, or entire netlists. Much of the necessary knowledge for cunstring such databases is either hidden within the analog designer’s mind, or by extension in published articles. With the recent success in language processing, an opportunity for automatic sighting and analysis of data arises. In this work, experiments with language models will be conducted, with the goal of building a database of articles treating a specific subject in analog design.

(all the details are in the PDF)

Use CoreDSLPerf to model one or more of the following ISA Extensions + Microarchitecture Implementations:

• RISC-V P(acked) Extension (i.e. on RI5CY core)
• RISC-V V(ector) Extension (i.e. on ARA+Ariane, Vicuna, Spatz)
• RISCV-V B(itmanipulation) Extension (i.e. on RI5CY)
• PULP custom ISA Extensions, such as hardware loops, post-increment load/store, MAC,... (i.e. on RI5CY)
• Special vector extensions (i.e. Andestech D25F, Xuantie C906)

This project is proposed and conducted in cooperation with MINRES Technologies.

RISC-V is an open-source instruction set architecture (ISA), which has recently gained a lot of interest in both academia and commercial contexts. One of the key features of the RISC-V architecture is its flexibility, which, for instance, allows chip designers to add custom instructions to support their specific use cases. Further, due to its open-source character, designers are free to implement their own, customized RISC-V microarchitecture.

To fully utilize the flexibility of RISC-V, different design choices should be explored, in order to find the best suited solution. Such a so-called design space exploration (DSE) typically relies on abstract models of the actual hardware, which can be quickly modified to cover different design choices. As high execution speed is frequently of major importance for a processor, accuratly depicting the processor's performance is one of the key requirements for this type of models.

During this project, abstract performance models shall be generated for an existing RISC-V CPU, developted by MINRES Technologies, in order to evaluate its performance. To achieve this, the student will:

1. Integrate a tool-chain for performance modelling, developted at TUM, into the simulation environment of MINRES, in order to establish a common workflow.
2. Use the established workflow to generate abstract performance models of an existing RISC-V CPU, developted by MINRES.
3. Evaluate the accuracy of the generated models, by comparing their performance estimates with the actual performance of the CPU.

 This project requires

• A fundamental understanding of the functionality of processors and basic microarchitectural concepts
• Solid experience in object-oriented programming.
• Experience in programming with C++ and Python3 are a major benefit

M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.

The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.

Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.

• Interest in learning about symbolic evaluation and simplification
• Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
• Very good knowledge of Python
• Some experience with parser generators, ideally ANTLR4

Welcome to "Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge," a dynamic and hands-on internship designed to empower students in harnessing their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming innovative entrepreneurs in the realm of sensor and microsystem applications.

Overview:

In this practical internship, students will delve into the world of microsystems, exploring their components, functionalities, and potential applications. The focus will be on fostering creativity and teamwork as students work collaboratively to conceive, design, and prototype innovative solutions using sensors and microsystems.

Key Features:

Creative Exploration: Unlike traditional courses and internships, this one offers the freedom to choose and define your own technical challenge. Students will be encouraged to think outside the box, identify real-world problems, and propose solutions that leverage microsystems to enhance human-technology interactions.

Hands-On Prototyping: The heart of the internship lies in turning ideas into reality. Students will actively engage in the prototyping process, developing functional prototypes of their innovative concepts. Emphasis will be placed on understanding the practical aspects of sensor integration, actuation, and control electronics.

COSIMA Contest Preparation: The internship will align with the COSIMA contest requirements, preparing students to present their prototypes on the competition day. Guidance will be provided on creating impactful presentations that showcase the ingenuity and practicality of their solutions.

Go International: The winners of COSIMA will qualify to take part in the international iCAN competition. Guidance and preparation for the iCAN will be provided.

Entrepreneurial Mindset: Drawing inspiration from successful startups that emerged from COSIMA, the internship will instill an entrepreneurial mindset. Students will learn about the essentials of founding a startup, from business planning to pitching their ideas.

Us in the past:

Das war COSIMA 2023 (cosima-mems.de)

iCAN Wettbewerb 2023 (cosima-mems.de)

Sieger 2022 (cosima-mems.de)

Intermediate German and English language proficiency is required.

M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.

The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.

Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.

• Interest in learning about symbolic evaluation and simplification
• Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
• Very good knowledge of Python
• Some experience with parser generators, ideally ANTLR4

Welcome to "Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge," a dynamic and hands-on internship designed to empower students in harnessing their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming innovative entrepreneurs in the realm of sensor and microsystem applications.

Overview:

In this practical internship, students will delve into the world of microsystems, exploring their components, functionalities, and potential applications. The focus will be on fostering creativity and teamwork as students work collaboratively to conceive, design, and prototype innovative solutions using sensors and microsystems.

Key Features:

Creative Exploration: Unlike traditional courses and internships, this one offers the freedom to choose and define your own technical challenge. Students will be encouraged to think outside the box, identify real-world problems, and propose solutions that leverage microsystems to enhance human-technology interactions.

Hands-On Prototyping: The heart of the internship lies in turning ideas into reality. Students will actively engage in the prototyping process, developing functional prototypes of their innovative concepts. Emphasis will be placed on understanding the practical aspects of sensor integration, actuation, and control electronics.

COSIMA Contest Preparation: The internship will align with the COSIMA contest requirements, preparing students to present their prototypes on the competition day. Guidance will be provided on creating impactful presentations that showcase the ingenuity and practicality of their solutions.

Go International: The winners of COSIMA will qualify to take part in the international iCAN competition. Guidance and preparation for the iCAN will be provided.

Entrepreneurial Mindset: Drawing inspiration from successful startups that emerged from COSIMA, the internship will instill an entrepreneurial mindset. Students will learn about the essentials of founding a startup, from business planning to pitching their ideas.

Us in the past:

Das war COSIMA 2023 (cosima-mems.de)

iCAN Wettbewerb 2023 (cosima-mems.de)

Sieger 2022 (cosima-mems.de)

Intermediate German and English language proficiency is required.

Siehe beigefügten Aushang.

Use CoreDSLPerf to model one or more of the following ISA Extensions + Microarchitecture Implementations:

• RISC-V P(acked) Extension (i.e. on RI5CY core)
• RISC-V V(ector) Extension (i.e. on ARA+Ariane, Vicuna, Spatz)
• RISCV-V B(itmanipulation) Extension (i.e. on RI5CY)
• PULP custom ISA Extensions, such as hardware loops, post-increment load/store, MAC,... (i.e. on RI5CY)
• Special vector extensions (i.e. Andestech D25F, Xuantie C906)

This project is proposed and conducted in cooperation with MINRES Technologies.

RISC-V is an open-source instruction set architecture (ISA), which has recently gained a lot of interest in both academia and commercial contexts. One of the key features of the RISC-V architecture is its flexibility, which, for instance, allows chip designers to add custom instructions to support their specific use cases. Further, due to its open-source character, designers are free to implement their own, customized RISC-V microarchitecture.

To fully utilize the flexibility of RISC-V, different design choices should be explored, in order to find the best suited solution. Such a so-called design space exploration (DSE) typically relies on abstract models of the actual hardware, which can be quickly modified to cover different design choices. As high execution speed is frequently of major importance for a processor, accuratly depicting the processor's performance is one of the key requirements for this type of models.

During this project, abstract performance models shall be generated for an existing RISC-V CPU, developted by MINRES Technologies, in order to evaluate its performance. To achieve this, the student will:

1. Integrate a tool-chain for performance modelling, developted at TUM, into the simulation environment of MINRES, in order to establish a common workflow.
2. Use the established workflow to generate abstract performance models of an existing RISC-V CPU, developted by MINRES.
3. Evaluate the accuracy of the generated models, by comparing their performance estimates with the actual performance of the CPU.

 This project requires

• A fundamental understanding of the functionality of processors and basic microarchitectural concepts
• Solid experience in object-oriented programming.
• Experience in programming with C++ and Python3 are a major benefit

M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.

The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.

Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.

• Interest in learning about symbolic evaluation and simplification
• Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
• Very good knowledge of Python
• Some experience with parser generators, ideally ANTLR4

Welcome to "Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge," a dynamic and hands-on internship designed to empower students in harnessing their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming innovative entrepreneurs in the realm of sensor and microsystem applications.

Overview:

In this practical internship, students will delve into the world of microsystems, exploring their components, functionalities, and potential applications. The focus will be on fostering creativity and teamwork as students work collaboratively to conceive, design, and prototype innovative solutions using sensors and microsystems.

Key Features:

Creative Exploration: Unlike traditional courses and internships, this one offers the freedom to choose and define your own technical challenge. Students will be encouraged to think outside the box, identify real-world problems, and propose solutions that leverage microsystems to enhance human-technology interactions.

Hands-On Prototyping: The heart of the internship lies in turning ideas into reality. Students will actively engage in the prototyping process, developing functional prototypes of their innovative concepts. Emphasis will be placed on understanding the practical aspects of sensor integration, actuation, and control electronics.

COSIMA Contest Preparation: The internship will align with the COSIMA contest requirements, preparing students to present their prototypes on the competition day. Guidance will be provided on creating impactful presentations that showcase the ingenuity and practicality of their solutions.

Go International: The winners of COSIMA will qualify to take part in the international iCAN competition. Guidance and preparation for the iCAN will be provided.

Entrepreneurial Mindset: Drawing inspiration from successful startups that emerged from COSIMA, the internship will instill an entrepreneurial mindset. Students will learn about the essentials of founding a startup, from business planning to pitching their ideas.

Us in the past:

Das war COSIMA 2023 (cosima-mems.de)

iCAN Wettbewerb 2023 (cosima-mems.de)

Sieger 2022 (cosima-mems.de)

Intermediate German and English language proficiency is required.

Siehe beigefügten Aushang.

M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.

The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.

Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.

• Interest in learning about symbolic evaluation and simplification
• Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
• Very good knowledge of Python
• Some experience with parser generators, ideally ANTLR4

Siehe beigefügten Aushang.

Use CoreDSLPerf to model one or more of the following ISA Extensions + Microarchitecture Implementations:

• RISC-V P(acked) Extension (i.e. on RI5CY core)
• RISC-V V(ector) Extension (i.e. on ARA+Ariane, Vicuna, Spatz)
• RISCV-V B(itmanipulation) Extension (i.e. on RI5CY)
• PULP custom ISA Extensions, such as hardware loops, post-increment load/store, MAC,... (i.e. on RI5CY)
• Special vector extensions (i.e. Andestech D25F, Xuantie C906)