Synthesis of Digital Systems

Lecturer (assistant)
Number0000003198
Type
Duration3 SWS
TermSommersemester 2024
Language of instructionEnglish
Position within curriculaSee TUMonline

Admission information

See TUMonline
Note: Note: Maximal number of participants is 50. Registration for lecture and lab is done via the Reihung Masterpraktika. the lecture and lab have to be done together. Participation at the scheduled lab session is mandatory. Students from the waiting list can participate if registered students do not show up.

Objectives

After participation, the students know the basic design steps of digital systems. They understand the difference of implementing a task in hardware or as software program. They know the compilation steps and understand static code analysis and optimization. The students understand the theory of high-level synthesis with focus on algorithms for scheduling and binding. The students can apply these algorithms by generating RTL descriptions for small code examples. They can apply an industrial high level synthesis after the practical sessions. Additionally, the basic concepts of SW compilers and code execution are understood by the students after participation. The students are able to apply compilation steps on small code examples to generate optimized assembly code. The students obtain the practical skills to write embedded C program and to implement a SW/HW interface. The students know some basic system modeling methodology and can apply load balancing methods.

Description

Summer semester: Course will be in German language in presence, exam will be in presence in English and German. Laboratory virtual/online. The following topics are covered during the lecture and exercises: - Introduction to the synthesis steps and the design flow of digital systems - Static code analysis and code optimisation - High-level hardware synthesis including data path design, ASAP-, ALAP- and List-Scheduling, binding with Left-Edge algorithm, control path design - Software compilation and execution including compilation steps, ARM assembly code generation, instruction set architectures, register allocation, RISC pipeline, data and control hazards, estimation of execution times - Introduction to HW/SW interfaces, system models and load balancing algorithms The following applications are covered in the practical lab sessions: - Hands-on training on an industrial high level synthesis (HLS) tool - Implementation of a HW peripheral using HLS - Implementation of the HW/SW interface - Synthesis and execution on an FPGA board

Prerequisites

The participation in a VHDL lab before this lecture is encouraged. Basic knowledge of C programming and assembly code is desired.

Teaching and learning methods

The lecture is divided into lecture, exercise and lab sessions (50%), as well as self-study time (50%). During lecture and exercises, subjects are taught with a mix of methods. This includes frontal methods such as presentations on specific topics and assignments derived on the black board as well as various activating methods ranging from individual assignments and team assignments to team discussions. The hands-on lab sessions are usually worked on in small teams. The lab sessions are strongly aligned with the lecture's topics to ensure that the theory learned during lecture can be applied to practical design problems. For this, modern EDA tools are used. Additionally, individual and independent work is done on practical assignments in the self-study time. An e-learning platform is used to provide the learning materials to the students.

Examination

The exam consists of two parts: A written exam that includes questions and problems on the material that is taught in the lecture, exercises and lab sessions. Three assignments during the semester to test practical skills taught during the lab sessions and to test the ability to connect these with the theory taught during the lecture. The final grade is computed as: - 75 % grade in written exam (90 min., open book policy) - 25 % grade for the three practical assignments The two parts of the exam ease the effort of the students at the end of the semester and focus on the difference in skills obtained in the lecture, exercise and lab.

Recommended literature

* Philippe Coussy, Adam Morawiec: High-level synthesis from Algorithm to digital circuit, Springer 2008 * Alfred Aho, Monica Lam, Ravi Sethi, Jeffrey Ullman: Compilers Principles, Techniques & Tools, Pearson Education 2007

Links


All courses

Bachelorbereich: BSc-EI, MSE, BSEDE

  WS SS Diskrete Mathematik für Ingenieure (BSEI, EI00460) Discrete Mathematics for Engineers (BSEDE ) (Schlichtmann) (Januar)
WS SS Entwurf digitaler Systeme mit VHDL u. System C (BSEI, EI0690) (Ecker)
  SS Entwurfsverfahren für integrierte Schaltungen (MSE, EI43811) (Schlichtmann)
WS   Methoden der Unternehmensführung (BSEI, EI0481) (Weigel)
WS   Praktikum System- und Schaltungstechnik (BSEI, EI0664) (Schlichtmann et al.)
  SS Schaltungssimulation (BSEI, EI06691) (Gräb/Schlichtmann)

 

Masterbereich: MSc-EI, MSCE, ICD

  SS Advanced Topics in Communication Electronics (MSCE, MSEI, EI79002)  
WS   Electronic Design Automation (MSCE, MSEI, EI70610) (B. Li, Tseng)  
WS   Design Methodology and Automation (ICD) (Schlichtmann) (Nov)  
WS SS Machine Learning: Methods and Tools (MSCE, MSEI, EI71040) (Ecker)  
WS SS SS Mathematical Methods of Circuit Design (MSCE, MSEI, EI74042) (Gräb) Simulation and Optimization of Analog Circuits (ICD) (Gräb) (Mai)  
WS   Mixed Integer Programming and Graph Algorithms in Engineering Problems (MSCE, MSEI, EI71059) (Tseng)  
WS SS Numerische Methoden der Elektrotechnik (MSEI, EI70440) (Schlichtmann oder Gräb)  
WS WS SS Seminar VLSI-Entwurfsverfahren (MSEI, EI7750) (Schlichtmann/Müller-Gritschneder) Seminar on Topics in Electronic Design Automation (MSCE, EI77502) (Schlichtmann/Müller-Gritschneder)  
WS SS Synthesis of Digital Systems (MSCE, MSEI, EI70640) (Müller-Gritschneder)  
WS   Testing Digital Circuits (MSCE, MSEI, EI50141) (Otterstedt)  
WS   Timing of Digital Circuits (MSCE, MSEI, EI70550) (B. Li, Zhang)  
WS SS VHDL System Design Laboratory (MSCE, MSEI, EI7403) (Schlichtmann)  

MSE: Munich School of Engineering (TUM)

BSEDE: Bachelor of Science in Electronics and Data Engineering (TUM-Asia)

ICD: Master of Science in Integrated Circuit Design (TUM-Asia)

MSCE: Master of Science in Communications Engineering (TUM)

MSEI: Master of Science in Elektrotechnik und Informationstechnik

BSEI: Bachelor of Science in Elektrotechnik und Informationstechnik

Aktuelle Infos zur Lehre/Current information on teaching: https://www.tum.de/die-tum/aktuelles/coronavirus/studium/, www.ei.tum.de