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Doctoral Research Seminar on ""COMPAS: Compiler-Assisted Software-Implemented Hardware Fault Tolerance for RISC-V"


This semester's last research seminar will be on "COMPAS: Compiler-Assisted Software-Implemented Hardware Fault Tolerance for RISC-V" by Uzair Sharif, TUM Chair of Electronic Design Automation (Prof. Schlichtmann).

Abstract:
Safety-critical systems have to ensure safe operation in the face of random hardware errors. To meet these resilience requirements in embedded systems, Software Implemented Hardware Fault Tolerance (SIHFT) methods offer an attractive solution. Though SIHFT research is mature, porting such methods to a specific processor architecture poses a challenge. In this talk, we present our open-source COMPAS compiler framework that realizes state-of-the-art SIHFT error-detection approaches targeting RISC-V processors. SIHFT transformations for major instruction classes such as loads, stores, branches etc. are described in terms of RISC-V code. Further, we present our RTL fault injection analysis to accurately quantify soft error resilience of RISC-V programs. The results demonstrate enhanced resilience of RISC-V software hardened with COMPAS transformations, that is in line with prior works.

Time: July 25th, 2022 11:00-12:00 online.