Picture of Alexander Hepp

Alexander Hepp

Technical University of Munich

Place of employment

Chair of Security in Information Technology (Prof. Sigl)

Work:
Theresienstr. 90(0101)/1.ZG
80333 München

Room: N1007ZG

 

Research Interests

  • Hardware trojan design/identification
  • Netlist reverse engineering
  • Neuro engineering

Teaching

Blockpraktikum C++

Lecturer (assistant)
Number0000002124
Type
Duration4 SWS
TermSommersemester 2024
Language of instructionGerman
Position within curriculaSee TUMonline
DatesSee TUMonline

Admission information

See TUMonline
Note: Bachelorstudiengang EI; Voraussetzung für die Teilnahme ist die Anmeldung zur Prüfung

Objectives

At the end of the module students have acquired basics and advanced knowledge on the programming language C++ and are able to practically apply their knowledge. The students are able to create Template classes and functions and can apply the Standard Template Library (STL) in C++ programming tasks. The students have understood the importance of well readable and well documented code and are able to create C++ code accordingly. Furthermore, the students have understood the concepts of object oriented programming (OOP) and are able to create object oriented programs - using classes, inheritance, polymorphism, virtual functions, etc. - in C++.

Description

During the studies of electrical engineering, it is highly relevant to acquire programming skills in an industry-standard, widely used programming language, like C++. This lab course is intended to give students the chance to learn C++ during the semester breaks in an intensive course. There are two phases: in the first, fundamental concepts of C++, like objects, classes, and templates, are taught in lectures followed by hands-on sessions. This phase has a duration of 2 weeks (full time). Tutors will be available for answering questions during the hands-on sessions. In the second phase, the knowledge should be improved by conducting a programming project in small groups. This project must be finished within 2 weeks and can be conducted at home or in the rooms of the institute. The students are examined by a written and by an oral examination.

Prerequisites

Grundpraktikum C, Algorithmen und Datenstrukturen or comparable courses

Teaching and learning methods

Lectures with hands-on sessions in the lab in the first phase, self-study tasks in the second phase

Examination

Considering the learning objectives, the exam is split into the following parts: - The knowledge from the lecture and the practical exercises in the first part is examined in the second part of the four weeks block by a written exam (60 minutes). - The capability to use the knowledge in practice is shown by a practical project. - The quality of the practical work is shown by a presentation and examined by targeted oral questions onto the delivered C++-implementation at the end of the practical course (approx. 30 minutes). The final grad is calculated from the written exam (60%) and the presentation cum oral questions (40%). The practical project must be graded as "passed".

Recommended literature

Programming - Principles and Practice Using C++, Addison-Wesley ISBN 978-0321543721. December 2008. The C++ Programming Language (Third Edition and Special Edition) Addison-Wesley, ISBN 0-201-88954-4 and 0-201-70073-5. Fundamental Algorithms The Art of Computer Programming Addison-Wesley, ISBN 0-201-89683-4

Links

Open positions for students

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Bachelor's Theses

Performant Trace Recording with Streaming Mode

Description

Oscilloscope Trace Recording requires quick data processing, low-level driver API handling, high level post-processing, all highly configurable for scientific applications. To increase performance on the oscilloscope side, it is important to use the streaming mode, that is near real-time recording from the scope. This creates tight constraints for data processing on the computer side, as Samples will arrive with 1.2 GBit/s

In this thesis, you will continue development of a skeleton application for this task, written in Rust

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a System-Level Programming language such as C/C++/Rust etc. as a baseline for programming abilities
  • Basic to intermediate knowledge of Rust, to be able to actually enhance the status quo in Rust. Learning on the job is possible, probably.
  • In the optimum case experience with (Side-Channel) Trace Measurement, to understand the environment of the program

 

 

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Supervisor:

Alexander Hepp

Needles in Haystacks

Description

In a world of multinational production chains, hardware trojans inserted by untrusted third parties are an emerging threat for the security of integrated circuits.

Detection methods have come a long way, but still cannot archieve good performance in realistic scenarios.

During this thesis, you will implement and improve an existing hardware trojan detection method.

 

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a High-Level Programming language such as python, because machine learning and reverse engineering tools build on this
  • Basic to intermediate knowledge of a hardware description language such as vhdl or verilog for understanding the trojan samples
  • Basic knowledge in design/architecture of hardware design to understand  trojan location and insertion.

 

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Supervisor:

Alexander Hepp

Exploring netlist representations for netlist RE

Description

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

 

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a python to use our existing framework
  • Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
  • Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

 

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Supervisor:

Alexander Hepp

Developing tools for chip reverse engineering

Description

In reverse engineering of digital circuits, automation helps the researcher to cope with the complexity of input data. Many tools have to be tailored to the specific research focus and help to use standard tools made for IC design.

For example, the researcher might receive a netlist synthesized with a cell library that is not available. In this case, it would be necessary to reverse-engineer the library, eg. based on the cell and pin names, and create a bare dummy-library that allows to parse the netlist with general purpose synthesis tools.

In this engineering internship, you'll work closely with a researcher in the reverse engineering field and create well-designed automation tools for netlist reverse engineering.

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in any High-Level Programming language such as python, c, c++, rust, perl, etc.
  • A very basic knowledge of chip design in order to know what data you are dealing with
  • Creativity and interest for details in oder to create a good concept of the tool you want to implement

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

Supervisor:

Alexander Hepp

Implementation of Hardware Trojans

Description

In a world of multinational production chains, hardware trojans inserted by untrusted third parties are an emerging threat for the security of integrated circuits.

In order to develop methods for hardware trojan detection, specimens of hardware trojans are needed. Unfortunately, the variety of specimen currently available is very low.

During this thesis, you will implement a hardware trojan for a FPGA or ASIC circuit.

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a High-Level Programming language such as python for designing an interface
  • Basic to intermediate knowledge of a hardware description language such as vhdl or verilog for designing the trojan
  • Basic knowledge in design/architecture of cryptographic algorithms / CPUs to know where a trojan might be injected

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

Supervisor:

Alexander Hepp

Master's Theses

Hide and Seek

Description

Side-Channel based exfiltration of cryptographic secrets is an long-standing and ever occuring problem when implementing cryptographic algorithms under the assumption of real hardware.

Established formally-proved countermeasures against side channels do not provide definite protection. In the real world, a multitude of hardening measures are necessary to provide in depth-protection.

In this thesis, you will try and compare different methods of in-depth protection.

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a High-Level Programming language such as python for measurement automisation etc.
  • Basic to intermediate knowledge of a hardware description language such as vhdl or verilog for designing the hardening measures
  • In the optimum case experience with FPGAs to try the measures in the real world.
  • Knowledge in design/architecture of cryptographic algorithms to know when and how to do the hardening.

 

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Supervisor:

Alexander Hepp

Needles in Haystacks

Description

In a world of multinational production chains, hardware trojans inserted by untrusted third parties are an emerging threat for the security of integrated circuits.

Detection methods have come a long way, but still cannot archieve good performance in realistic scenarios.

During this thesis, you will implement and improve an existing hardware trojan detection method.

 

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a High-Level Programming language such as python, because machine learning and reverse engineering tools build on this
  • Basic to intermediate knowledge of a hardware description language such as vhdl or verilog for understanding the trojan samples
  • Basic knowledge in design/architecture of hardware design to understand  trojan location and insertion.

 

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Supervisor:

Alexander Hepp

Exploring netlist representations for netlist RE

Description

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

 

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a python to use our existing framework
  • Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
  • Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

 

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Supervisor:

Alexander Hepp

Implementation of Hardware Trojans

Description

In a world of multinational production chains, hardware trojans inserted by untrusted third parties are an emerging threat for the security of integrated circuits.

In order to develop methods for hardware trojan detection, specimens of hardware trojans are needed. Unfortunately, the variety of specimen currently available is very low.

During this thesis, you will implement a hardware trojan for a FPGA or ASIC circuit.

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a High-Level Programming language such as python for designing an interface
  • Basic to intermediate knowledge of a hardware description language such as vhdl or verilog for designing the trojan
  • Basic knowledge in design/architecture of cryptographic algorithms / CPUs to know where a trojan might be injected

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

Supervisor:

Alexander Hepp

Interdisciplinary Projects

Performant Trace Recording with Streaming Mode

Description

Oscilloscope Trace Recording requires quick data processing, low-level driver API handling, high level post-processing, all highly configurable for scientific applications. To increase performance on the oscilloscope side, it is important to use the streaming mode, that is near real-time recording from the scope. This creates tight constraints for data processing on the computer side, as Samples will arrive with 1.2 GBit/s

In this thesis, you will continue development of a skeleton application for this task, written in Rust

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a System-Level Programming language such as C/C++/Rust etc. as a baseline for programming abilities
  • Basic to intermediate knowledge of Rust, to be able to actually enhance the status quo in Rust. Learning on the job is possible, probably.
  • In the optimum case experience with (Side-Channel) Trace Measurement, to understand the environment of the program

 

 

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Supervisor:

Alexander Hepp

Developing tools for chip reverse engineering

Description

In reverse engineering of digital circuits, automation helps the researcher to cope with the complexity of input data. Many tools have to be tailored to the specific research focus and help to use standard tools made for IC design.

For example, the researcher might receive a netlist synthesized with a cell library that is not available. In this case, it would be necessary to reverse-engineer the library, eg. based on the cell and pin names, and create a bare dummy-library that allows to parse the netlist with general purpose synthesis tools.

In this engineering internship, you'll work closely with a researcher in the reverse engineering field and create well-designed automation tools for netlist reverse engineering.

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in any High-Level Programming language such as python, c, c++, rust, perl, etc.
  • A very basic knowledge of chip design in order to know what data you are dealing with
  • Creativity and interest for details in oder to create a good concept of the tool you want to implement

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

Supervisor:

Alexander Hepp

Research Internships (Forschungspraxis)

Performant Trace Recording with Streaming Mode

Description

Oscilloscope Trace Recording requires quick data processing, low-level driver API handling, high level post-processing, all highly configurable for scientific applications. To increase performance on the oscilloscope side, it is important to use the streaming mode, that is near real-time recording from the scope. This creates tight constraints for data processing on the computer side, as Samples will arrive with 1.2 GBit/s

In this thesis, you will continue development of a skeleton application for this task, written in Rust

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a System-Level Programming language such as C/C++/Rust etc. as a baseline for programming abilities
  • Basic to intermediate knowledge of Rust, to be able to actually enhance the status quo in Rust. Learning on the job is possible, probably.
  • In the optimum case experience with (Side-Channel) Trace Measurement, to understand the environment of the program

 

 

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Supervisor:

Alexander Hepp

Hide and Seek

Description

Side-Channel based exfiltration of cryptographic secrets is an long-standing and ever occuring problem when implementing cryptographic algorithms under the assumption of real hardware.

Established formally-proved countermeasures against side channels do not provide definite protection. In the real world, a multitude of hardening measures are necessary to provide in depth-protection.

In this thesis, you will try and compare different methods of in-depth protection.

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a High-Level Programming language such as python for measurement automisation etc.
  • Basic to intermediate knowledge of a hardware description language such as vhdl or verilog for designing the hardening measures
  • In the optimum case experience with FPGAs to try the measures in the real world.
  • Knowledge in design/architecture of cryptographic algorithms to know when and how to do the hardening.

 

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Supervisor:

Alexander Hepp

Needles in Haystacks

Description

In a world of multinational production chains, hardware trojans inserted by untrusted third parties are an emerging threat for the security of integrated circuits.

Detection methods have come a long way, but still cannot archieve good performance in realistic scenarios.

During this thesis, you will implement and improve an existing hardware trojan detection method.

 

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a High-Level Programming language such as python, because machine learning and reverse engineering tools build on this
  • Basic to intermediate knowledge of a hardware description language such as vhdl or verilog for understanding the trojan samples
  • Basic knowledge in design/architecture of hardware design to understand  trojan location and insertion.

 

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Supervisor:

Alexander Hepp

Exploring netlist representations for netlist RE

Description

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

 

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a python to use our existing framework
  • Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
  • Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

 

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Supervisor:

Alexander Hepp

Implementation of Hardware Trojans

Description

In a world of multinational production chains, hardware trojans inserted by untrusted third parties are an emerging threat for the security of integrated circuits.

In order to develop methods for hardware trojan detection, specimens of hardware trojans are needed. Unfortunately, the variety of specimen currently available is very low.

During this thesis, you will implement a hardware trojan for a FPGA or ASIC circuit.

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a High-Level Programming language such as python for designing an interface
  • Basic to intermediate knowledge of a hardware description language such as vhdl or verilog for designing the trojan
  • Basic knowledge in design/architecture of cryptographic algorithms / CPUs to know where a trojan might be injected

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

Supervisor:

Alexander Hepp

Student Assistant Jobs

Performant Trace Recording with Streaming Mode

Description

Oscilloscope Trace Recording requires quick data processing, low-level driver API handling, high level post-processing, all highly configurable for scientific applications. To increase performance on the oscilloscope side, it is important to use the streaming mode, that is near real-time recording from the scope. This creates tight constraints for data processing on the computer side, as Samples will arrive with 1.2 GBit/s

In this thesis, you will continue development of a skeleton application for this task, written in Rust

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a System-Level Programming language such as C/C++/Rust etc. as a baseline for programming abilities
  • Basic to intermediate knowledge of Rust, to be able to actually enhance the status quo in Rust. Learning on the job is possible, probably.
  • In the optimum case experience with (Side-Channel) Trace Measurement, to understand the environment of the program

 

 

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Supervisor:

Alexander Hepp

Exploring netlist representations for netlist RE

Description

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

 

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in a python to use our existing framework
  • Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
  • Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

 

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

 

Supervisor:

Alexander Hepp

Developing tools for chip reverse engineering

Description

In reverse engineering of digital circuits, automation helps the researcher to cope with the complexity of input data. Many tools have to be tailored to the specific research focus and help to use standard tools made for IC design.

For example, the researcher might receive a netlist synthesized with a cell library that is not available. In this case, it would be necessary to reverse-engineer the library, eg. based on the cell and pin names, and create a bare dummy-library that allows to parse the netlist with general purpose synthesis tools.

In this engineering internship, you'll work closely with a researcher in the reverse engineering field and create well-designed automation tools for netlist reverse engineering.

Prerequisites

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

  • Sufficient knowledge in any High-Level Programming language such as python, c, c++, rust, perl, etc.
  • A very basic knowledge of chip design in order to know what data you are dealing with
  • Creativity and interest for details in oder to create a good concept of the tool you want to implement

Contact

If you are interested in this topic, don't hesitate to ask for an appointment via

alex.hepp@tum.de

Please include a grade report and a CV, so I can evaluate different focus areas to fit your experience.

Supervisor:

Alexander Hepp

Current Publications

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2024

  • Brunner, Michaela and Lee, Hye Hyun and Hepp, Alexander and Baehr, Johanna and Sigl, Georg: Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong Track. 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS), 2024Kielce, Poland more… BibTeX Full text ( DOI )

2022

  • Aksoy, Levent and Hepp, Alexander and Baehr, Johanna and Pagliarini, Samuel: Hardware Obfuscation of Digital FIR Filters. 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, IEEE, 2022Prague, Czech Republic, 68-73 more… BibTeX Full text ( DOI )
  • Baehr, Johanna and Hepp, Alexander and Brunner, Michaela and Malenko, Maja and Sigl, Georg: Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis. Euromicro Conference on Digital System Design DSD, 2022Maspalomas, Gran Canarias, Spain more… BibTeX
  • Brunner, Michaela and Hepp, Alexander and Baehr, Johanna and Sigl, Georg: Toward a Human-Readable State Machine Extraction. ACM Trans. Des. Autom. Electron. Syst. 27 (6), 2022 more… BibTeX Full text ( DOI )
  • Hepp, Alexander and Baehr, Johanna and Sigl, Georg: Golden Model-Free Hardware Trojan Detection by Classification of Netlist Module Graphs. Design, Automation and Test in Europe Conference, IEEE, 2022Antwerp, Belgium, 1317-1322 more… BibTeX Full text ( DOI )
  • Hepp, Alexander and Perez, Tiago and Pagliarini, Samuel and Sigl, Georg: A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts. Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design ICCAD (ICCAD '22), Association for Computing Machinery, 2022 more… BibTeX Full text ( DOI )
  • Lippmann, Bernhard and Ludwig, Matthias and Mutter, Johannes and Bette, Ann-Christin and Hepp, Alexander and Baehr, Johanna and Rasche, Martin and Kellermann, Oliver and Gieser, Horst and Zweifel, Tobias and Kovac, Nicola: Physical and Functional Reverse Engineering Challenges for Advanced Semiconductor Solutions. 2022 Design, Automation & Test in Europe Conference & Exhibition DATE, IEEE, 2022Antwerp, Belgium more… BibTeX
  • Weber, Selina and Baehr, Johanna and Hepp, Alexander and Sigl, Georg: Analysis of Graph-based Partitioning Algorithms and Partitioning Metrics for Hardware Reverse Engineering. 11th International Workshop on Security Proofs for Embedded Systems (PROOFS), 2022Leuven, Belgium more… BibTeX

2021

  • Hepp, Alexander and Sigl, Georg: Tapeout of a RISC-V Crypto Chip with Hardware Trojans: A Case-Study on Trojan Design and Pre-Silicon Detectability. Proceedings of the 18th ACM International Conference on Computing Frontiers (CF '21), Association for Computing Machinery, 2021Virtual: Catania, Italy more… BibTeX Full text ( DOI )
  • Ludwig, Matthias and Hepp, Alexander and Brunner, Michaela and Baehr, Johanna: CRESS: Framework for Vulnerability Assessment of Attack Scenarios in Hardware Reverse Engineering. 2021 IEEE Physical Assurance and Inspection of Electronics (PAINE), 2021Washington DC, US more… BibTeX Full text ( DOI )

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