Oscilloscope Trace Recording requires quick data processing, low-level driver API handling, high level post-processing, all highly configurable for scientific applications. To increase performance on the oscilloscope side, it is important to use the streaming mode, that is near real-time recording from the scope. This creates tight constraints for data processing on the computer side, as Samples will arrive with 1.2 GBit/s

In this thesis, you will continue development of a skeleton application for this task, written in Rust

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a System-Level Programming language such as C/C++/Rust etc. as a baseline for programming abilities
• Basic to intermediate knowledge of Rust, to be able to actually enhance the status quo in Rust. Learning on the job is possible, probably.
• In the optimum case experience with (Side-Channel) Trace Measurement, to understand the environment of the program

In a world of multinational production chains, hardware trojans inserted by untrusted third parties are an emerging threat for the security of integrated circuits.

Detection methods have come a long way, but still cannot archieve good performance in realistic scenarios.

During this thesis, you will implement and improve an existing hardware trojan detection method.

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a High-Level Programming language such as python, because machine learning and reverse engineering tools build on this
• Basic to intermediate knowledge of a hardware description language such as vhdl or verilog for understanding the trojan samples
• Basic knowledge in design/architecture of hardware design to understand  trojan location and insertion.

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a python to use our existing framework
• Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
• Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

In reverse engineering of digital circuits, automation helps the researcher to cope with the complexity of input data. Many tools have to be tailored to the specific research focus and help to use standard tools made for IC design.

For example, the researcher might receive a netlist synthesized with a cell library that is not available. In this case, it would be necessary to reverse-engineer the library, eg. based on the cell and pin names, and create a bare dummy-library that allows to parse the netlist with general purpose synthesis tools.

In this engineering internship, you'll work closely with a researcher in the reverse engineering field and create well-designed automation tools for netlist reverse engineering.

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in any High-Level Programming language such as python, c, c++, rust, perl, etc.
• A very basic knowledge of chip design in order to know what data you are dealing with
• Creativity and interest for details in oder to create a good concept of the tool you want to implement

In a world of multinational production chains, hardware trojans inserted by untrusted third parties are an emerging threat for the security of integrated circuits.

In order to develop methods for hardware trojan detection, specimens of hardware trojans are needed. Unfortunately, the variety of specimen currently available is very low.

During this thesis, you will implement a hardware trojan for a FPGA or ASIC circuit.

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a High-Level Programming language such as python for designing an interface
• Basic to intermediate knowledge of a hardware description language such as vhdl or verilog for designing the trojan
• Basic knowledge in design/architecture of cryptographic algorithms / CPUs to know where a trojan might be injected

Side-Channel based exfiltration of cryptographic secrets is an long-standing and ever occuring problem when implementing cryptographic algorithms under the assumption of real hardware.

Established formally-proved countermeasures against side channels do not provide definite protection. In the real world, a multitude of hardening measures are necessary to provide in depth-protection.

In this thesis, you will try and compare different methods of in-depth protection.

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a High-Level Programming language such as python for measurement automisation etc.
• Basic to intermediate knowledge of a hardware description language such as vhdl or verilog for designing the hardening measures
• In the optimum case experience with FPGAs to try the measures in the real world.
• Knowledge in design/architecture of cryptographic algorithms to know when and how to do the hardening.

In a world of multinational production chains, hardware trojans inserted by untrusted third parties are an emerging threat for the security of integrated circuits.

Detection methods have come a long way, but still cannot archieve good performance in realistic scenarios.

During this thesis, you will implement and improve an existing hardware trojan detection method.

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a High-Level Programming language such as python, because machine learning and reverse engineering tools build on this
• Basic to intermediate knowledge of a hardware description language such as vhdl or verilog for understanding the trojan samples
• Basic knowledge in design/architecture of hardware design to understand  trojan location and insertion.

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a python to use our existing framework
• Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
• Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

In a world of multinational production chains, hardware trojans inserted by untrusted third parties are an emerging threat for the security of integrated circuits.

In order to develop methods for hardware trojan detection, specimens of hardware trojans are needed. Unfortunately, the variety of specimen currently available is very low.

During this thesis, you will implement a hardware trojan for a FPGA or ASIC circuit.

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a High-Level Programming language such as python for designing an interface
• Basic to intermediate knowledge of a hardware description language such as vhdl or verilog for designing the trojan
• Basic knowledge in design/architecture of cryptographic algorithms / CPUs to know where a trojan might be injected

Oscilloscope Trace Recording requires quick data processing, low-level driver API handling, high level post-processing, all highly configurable for scientific applications. To increase performance on the oscilloscope side, it is important to use the streaming mode, that is near real-time recording from the scope. This creates tight constraints for data processing on the computer side, as Samples will arrive with 1.2 GBit/s

In this thesis, you will continue development of a skeleton application for this task, written in Rust

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a System-Level Programming language such as C/C++/Rust etc. as a baseline for programming abilities
• Basic to intermediate knowledge of Rust, to be able to actually enhance the status quo in Rust. Learning on the job is possible, probably.
• In the optimum case experience with (Side-Channel) Trace Measurement, to understand the environment of the program

In reverse engineering of digital circuits, automation helps the researcher to cope with the complexity of input data. Many tools have to be tailored to the specific research focus and help to use standard tools made for IC design.

For example, the researcher might receive a netlist synthesized with a cell library that is not available. In this case, it would be necessary to reverse-engineer the library, eg. based on the cell and pin names, and create a bare dummy-library that allows to parse the netlist with general purpose synthesis tools.

In this engineering internship, you'll work closely with a researcher in the reverse engineering field and create well-designed automation tools for netlist reverse engineering.

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in any High-Level Programming language such as python, c, c++, rust, perl, etc.
• A very basic knowledge of chip design in order to know what data you are dealing with
• Creativity and interest for details in oder to create a good concept of the tool you want to implement

Oscilloscope Trace Recording requires quick data processing, low-level driver API handling, high level post-processing, all highly configurable for scientific applications. To increase performance on the oscilloscope side, it is important to use the streaming mode, that is near real-time recording from the scope. This creates tight constraints for data processing on the computer side, as Samples will arrive with 1.2 GBit/s

In this thesis, you will continue development of a skeleton application for this task, written in Rust

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a System-Level Programming language such as C/C++/Rust etc. as a baseline for programming abilities
• Basic to intermediate knowledge of Rust, to be able to actually enhance the status quo in Rust. Learning on the job is possible, probably.
• In the optimum case experience with (Side-Channel) Trace Measurement, to understand the environment of the program

Side-Channel based exfiltration of cryptographic secrets is an long-standing and ever occuring problem when implementing cryptographic algorithms under the assumption of real hardware.

Established formally-proved countermeasures against side channels do not provide definite protection. In the real world, a multitude of hardening measures are necessary to provide in depth-protection.

In this thesis, you will try and compare different methods of in-depth protection.

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a High-Level Programming language such as python for measurement automisation etc.
• Basic to intermediate knowledge of a hardware description language such as vhdl or verilog for designing the hardening measures
• In the optimum case experience with FPGAs to try the measures in the real world.
• Knowledge in design/architecture of cryptographic algorithms to know when and how to do the hardening.

In a world of multinational production chains, hardware trojans inserted by untrusted third parties are an emerging threat for the security of integrated circuits.

Detection methods have come a long way, but still cannot archieve good performance in realistic scenarios.

During this thesis, you will implement and improve an existing hardware trojan detection method.

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a High-Level Programming language such as python, because machine learning and reverse engineering tools build on this
• Basic to intermediate knowledge of a hardware description language such as vhdl or verilog for understanding the trojan samples
• Basic knowledge in design/architecture of hardware design to understand  trojan location and insertion.

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a python to use our existing framework
• Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
• Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

In a world of multinational production chains, hardware trojans inserted by untrusted third parties are an emerging threat for the security of integrated circuits.

In order to develop methods for hardware trojan detection, specimens of hardware trojans are needed. Unfortunately, the variety of specimen currently available is very low.

During this thesis, you will implement a hardware trojan for a FPGA or ASIC circuit.

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a High-Level Programming language such as python for designing an interface
• Basic to intermediate knowledge of a hardware description language such as vhdl or verilog for designing the trojan
• Basic knowledge in design/architecture of cryptographic algorithms / CPUs to know where a trojan might be injected

Oscilloscope Trace Recording requires quick data processing, low-level driver API handling, high level post-processing, all highly configurable for scientific applications. To increase performance on the oscilloscope side, it is important to use the streaming mode, that is near real-time recording from the scope. This creates tight constraints for data processing on the computer side, as Samples will arrive with 1.2 GBit/s

In this thesis, you will continue development of a skeleton application for this task, written in Rust

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a System-Level Programming language such as C/C++/Rust etc. as a baseline for programming abilities
• Basic to intermediate knowledge of Rust, to be able to actually enhance the status quo in Rust. Learning on the job is possible, probably.
• In the optimum case experience with (Side-Channel) Trace Measurement, to understand the environment of the program

Reverse engineering of silicon hardware designs is an interesting task for various applications in science and industry, such as patent infringement detection, security analysis or hardware trojan detection.

One of the most challenging tasks is to go from the flat netlist, that is a graph of logic gates and wires between them, to a high level description of the design.

In this work, you will analyze and compare different methods for representing a netlist and the benefits and problems when analyzing the netlist using the different representations

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in a python to use our existing framework
• Basic knowledge of a hardware description language such as vhdl or verilog to understand what you are analyzing
• Basic knowledge in graph theory, algorithms etc. to cope with problems on the way.

In reverse engineering of digital circuits, automation helps the researcher to cope with the complexity of input data. Many tools have to be tailored to the specific research focus and help to use standard tools made for IC design.

For example, the researcher might receive a netlist synthesized with a cell library that is not available. In this case, it would be necessary to reverse-engineer the library, eg. based on the cell and pin names, and create a bare dummy-library that allows to parse the netlist with general purpose synthesis tools.

In this engineering internship, you'll work closely with a researcher in the reverse engineering field and create well-designed automation tools for netlist reverse engineering.

The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about.

• Sufficient knowledge in any High-Level Programming language such as python, c, c++, rust, perl, etc.
• A very basic knowledge of chip design in order to know what data you are dealing with
• Creativity and interest for details in oder to create a good concept of the tool you want to implement