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Note: This lab is only available for students in the Master's program Microelectronics and Chip Design.

After successfully completing this module, students will have acquired the following skills:
- They are able to develop a hardware description for a complex digital circuit starting from an abstract description and considering given specifications and apply the necessary steps to translate it into a description at netlist level.
- They are able to analyze the algorithmic description as well as their derived hardware description with regard to potential improvements and use the results of this analysis to improve their circuit.
- They are able to develop tests and can use them to check the functional correctness and compliance with the specifications for the circuit at RTL and netlist level.
- They understand the principles (e.g. methods of moderation) of group work and project planning (e.g. project structure planning, creation of requirements catalogs and specifications) and can apply these to design a project in the field of circuit design.
- They can clearly present the design and optimization strategies used in the process of logical design to a specialist audience.

In this module, students work in groups to create an register transfer level (RTL) description of a circuit based on an algorithm and from that a gatelevel netlist of this circuit. As a starting point, the students receive a textual description of an algorithm from a current topic area (for example from the field of hardware security or hardware acceleration for artificial intelligence) as well as literature to familiarize themselves with the task. Depending on the relevant subject areas, students are also given specific objectives for the development of the hardware for these algorithms. Examples here could be the development of a design with the smallest possible surface area, the lowest possible power consumption or the lowest possible latency; objectives such as avoiding side-channel failure in circuits from the field of security can also be an objective.
Following the familiarization, the students first partition their design with regard to the division into hardware and software components and divide the complex design into manageable logical blocks, for example with the help of the Kactus 2 tool. For these blocks, the students develop an RTL description of the circuit. This is done using a hardware description language (VHDL, Verilog or SystemVerilog). In addition, students develop tests to ensure the functional correctness of their circuit and its sub-modules. These are developed in accordance with the Universal Verification Methodology (UVM), for example. Simulation tools from commercial providers such as Cadence, Siemens or Synopsys are used in the process of testing.
After successful testing, students synthesize their circuit into a gatelevel netlist with the help of a commercial design automation tool, such as those offered by Cadence or Synopsys, and use the corresponding tools from the same providers to prove that the circuit is functionally correct even after this step. The development or adaptation of scripts, e.g. in the language TCL, which is widely used in electronic design automation, is necessary for both steps. Students also check the synthesis reports of their circuit for compliance with specifications and optimize their circuit if necessary.
When synthesizing the RTL description, a so-called cell library is used, which may be subject to special confidentiality and licensing agreements in the case of commercial manufacturers and technologies used in today's industry. Students who wish to take advantage of the opportunity to have the developed chip manufactured after the second part of the practical course may have to sign a corresponding agreement. Students who do not wish to sign this agreement can alternatively use a cell library adapted for teaching or an open source alternative; the same learning outcomes are achieved; however, subsequent production cannot then be offered.
In addition to the technical aspects mentioned, students learn principles and techniques for project planning and project work (e.g. project structure planning, creation of requirements catalogs and specifications), as well as group work, such as the structural requirements for group work or the method of moderation.

HDL Chip Design Laboratory

The basics for the lab are taught in approximately two introductory seminars. In particular, the work steps to be carried out, the specifications to be achieved and the design tools used are presented. In approximately three further seminars, content relating to group work and project planning is taught. The internship project is carried out independently in small groups of approx. 5 students in the scope of self-study in free time allocation. There is a regular exchange with a supervisor in the form of approx. weekly seminars and individual support and tutorials in the lab room (e.g. personal support in solving difficult problems in individual design); in this context, problems of the groups with the design and project organization are discussed and solved together.

The academic achievement is shown in form of a project work (in a group of around 5 people) in which students demonstrate that they can develop a suitable RTL description based on an algorithmic description and a given specification and, from this, a netlist description of a digital circuit. In addition, functional tests for the design must be developed and successfully carried out.
The design steps and the tests must be documented. The written documentation of the design and tests must be submitted at the end of the module and comprises approximately 5 pages per student, in which the individual contributions to the project are presented. Successful completion of the individual subtask must be demonstrated in order to pass the coursework.
The project work also includes a presentation in which the students demonstrate that they can present and discuss the progress and results of the project in a clear manner and in way showing their expertise (in groups, approx. 20 - 25 minutes or approx. 5 minutes per student with subsequent discussion).

Suitable literature will be made available to students in the introductory course, depending on the project.