Bachelor's Theses
Graph-level Fusing of RISC-V Instructions using CoreDSL
RISCV, CoreDSL, Graph, ISS, ETISS, ISA
The RISC-V instruction set architecture (ISA) is popular due to its extensibility which allows vendors to add custom operations to their application-specific cores. However, proposing and evaluating new instructions usually involves many efforts. There already exist numerous high-level-synthesis (HLS) approaches to automate this procedures by identifying a programs performance bottleneck aka. the critical basic blocks in the Assembly code. Using graph algorithms on the dataflow graph, suitable subgraphs for fusing into a single instruction can be found. To evaluate the newly added instruction we use virtual prototyping tools based on the CoreDSL2 language.
Description
Task Description:
- Literature research (Survey the State of the Art)
- Familarize with used tools (CoreDSL2, ETISS, M2-ISA-R, LLVM)
- Implement instruction fusing methodology based on given RISC-V assembly function (Extract dataflow/dependency graph, detect MIMO subgraphs, generate Instruction in M2-ISA-R metamodel, convert instruction to CoreDSL2 syntax.
- Evaluation of new instructions using ETISS virtual prototype (Generate simulation architecture files, build ETISS, Generate LLVM patches for instruction, build LLVM, build target software, test target software)
- Optional: Develop heuristics to estimate resource overhead for RTL implementation of new instructions.
Related Work/Tools:
- https://llvm.org/pubs/2010-02-IPSJ-CustomInstruction.pdf
- https://www.comp.nus.edu.sg/~tulika/fpt10.pdf
- https://github.com/Minres/CoreDSL/wiki/CoreDSL-2-programmer's-manual
- https://riscv-europe.org/summit/2023/media/proceedings/posters/2023-06-07-Karsten-EMRICH-abstract.pdf
- https://github.com/tum-ei-eda/etiss
Prerequisites
- Experience with RISC-V Assembly
- Deep knowledge about Python programming
- Some experience with CMake for compiling C/C++ projects using GCC/Clang cross-compiler toolchains
- Mathematical understanding of graph partitioning algorithms
Contact
philipp.van-kempen@tum.de
Supervisor:
Porting OpenASIP Custom Operations to CoreDSL Syntax
OpenASIP, EDA, CoreDSL, RISC-V, LLVM
The RISC-V instruction set architecture (ISA) is popular due to its extensibility which allows vendors to add custom operations to their application-specific instruction set processors. Using HW/SW Co-Design approaches and High-level-Synthesis this process can be automated in some degree. There exist custom ASIP generation tools in industry (see Synopsis ASIP Designer and Codasip Studio) as well as open-source alternatives (OpenASIP2.0) from academia.
Description
The goal of this project ist to evaluate the large pool of custom operations supported by the OpenASIP2.0 Co-Design toolchain on our instruction set simulator (ISS) named ETISS using the CoreDSL ecosystem.
Steps:
- Literature Research
- Familiarize with involved tools (OpenASIP, CoreDSL, CoreDSL)
- Collect list of all custom OpenASIP operations
- Develop methodology for translating the custom OpenASIP operations to the CoreDSL syntax
- Generate ETISS architectures using the new instructions
- Evaluate/Test/Benchmark the custom operations
- Optional: Allow ETISS to be used as OpenASIP2.0 target architecture.
Related Literature/Tools:
- https://riscv-europe.org/summit/2023/media/proceedings/posters/2023-06-07-Karsten-EMRICH-abstract.pdf
- https://www.researchgate.net/profile/Ulf-Schlichtmann/publication/322673899_The_extendable_translating_instruction_set_simulator_ETISS_interlinked_with_an_MDA_framework_for_fast_RISC_prototyping/links/5a836128a6fdcc6f3eb28a47/The-extendable-translating-instruction-set-simulator-ETISS-interlinked-with-an-MDA-framework-for-fast-RISC-prototyping.pdf
- https://github.com/tum-ei-eda/etiss
- https://github.com/Minres/CoreDSL/wiki/CoreDSL-2-programmer's-manual
- http://openasip.org/release_2_0.html
- https://zenodo.org/records/6670559
- https://github.com/cpc/openasip
Prerequisites
- Experience with RISC-V ISA (Assembly & Microarchitecture)
- Deep knowledge about Python programming
- Moderate C/C++ experience
Contact
philipp.van-kempen@tum.de
Supervisor:
AST Simplification and Optimization for M2-ISA-R Models
Description
M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.
The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.
Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.
Prerequisites
- Interest in learning about symbolic evaluation and simplification
- Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
- Very good knowledge of Python
- Some experience with parser generators, ideally ANTLR4
Contact
karsten.emrich@tum.de
Supervisor:
Master's Theses
Graph-level Fusing of RISC-V Instructions using CoreDSL
RISCV, CoreDSL, Graph, ISS, ETISS, ISA
The RISC-V instruction set architecture (ISA) is popular due to its extensibility which allows vendors to add custom operations to their application-specific cores. However, proposing and evaluating new instructions usually involves many efforts. There already exist numerous high-level-synthesis (HLS) approaches to automate this procedures by identifying a programs performance bottleneck aka. the critical basic blocks in the Assembly code. Using graph algorithms on the dataflow graph, suitable subgraphs for fusing into a single instruction can be found. To evaluate the newly added instruction we use virtual prototyping tools based on the CoreDSL2 language.
Description
Task Description:
- Literature research (Survey the State of the Art)
- Familarize with used tools (CoreDSL2, ETISS, M2-ISA-R, LLVM)
- Implement instruction fusing methodology based on given RISC-V assembly function (Extract dataflow/dependency graph, detect MIMO subgraphs, generate Instruction in M2-ISA-R metamodel, convert instruction to CoreDSL2 syntax.
- Evaluation of new instructions using ETISS virtual prototype (Generate simulation architecture files, build ETISS, Generate LLVM patches for instruction, build LLVM, build target software, test target software)
- Optional: Develop heuristics to estimate resource overhead for RTL implementation of new instructions.
Related Work/Tools:
- https://llvm.org/pubs/2010-02-IPSJ-CustomInstruction.pdf
- https://www.comp.nus.edu.sg/~tulika/fpt10.pdf
- https://github.com/Minres/CoreDSL/wiki/CoreDSL-2-programmer's-manual
- https://riscv-europe.org/summit/2023/media/proceedings/posters/2023-06-07-Karsten-EMRICH-abstract.pdf
- https://github.com/tum-ei-eda/etiss
Prerequisites
- Experience with RISC-V Assembly
- Deep knowledge about Python programming
- Some experience with CMake for compiling C/C++ projects using GCC/Clang cross-compiler toolchains
- Mathematical understanding of graph partitioning algorithms
Contact
philipp.van-kempen@tum.de
Supervisor:
Virtual Prototype based Evaluation of RISC-V Vector Extension for Embedded Machine Learning
RISCV, ETISS, CoreDSL, Vector, SIMD
The open RISC-V instruction set architecture (ISA) is popular for its extensibility. New instruction extensions are developed by the community as well as industry and academia. The RISC-V V(ector) Extension offers a large variety of new instructions to allow data-level parallelism in numerous embedded devices. We use efficient virtual prototypes (VPs) to evaluate new ISA extensions before actually hardware becomes available which is an important aspect for HW/SW/ISA Co-design. In this project the RISC-V vector (RVV) instructions should be modeled in the CoreDSL2 description language to allow simulations with our instruction set simulator (ISS) ETISS. The baseline is an existing partial implementation based on an outdated version of the RVV specification. After the implemented instructions have been verified for correctness, the performance of the ISA extension should be evaluated using a set of benchmarks from the TinyML field.
Description
Steps:
- Literature research
- Setup toolset (CoreDSL2 + M2-ISA-R + ETISS + LLVM + MLonMCU + TVM + muRISCV-NN)
- Implement (or generate) RISC-V (Embedded) Vector Instructions in CoreDSL comparing 2 different Approaches
- (A) Using external softvector library implemented in C++
- (B) By writing all instruction behavior in CoreDSL syntax
- Generate ETISS Architectures to test and verify the vector instructions
- Run Benchmarks of vectorized programs on ETISS with MLonMCU tool
- Compare Approach (A) & (B) in terms of
- LoCs (CoreDSL & C++)
- Simulated MIPS
- Generation Runtime
- Difficulty
- …
- Optional: Integration of (Embedded) Vector Extension in TVM
- Using fixed/scalable vectors
- Autotuning with MetaScheduler
- Implement RVV-specific tensor instrinsics
Related Tools/Literature:
- https://github.com/riscv/riscv-v-spec
- https://github.com/tum-ei-eda/etiss
- https://ieeexplore.ieee.org/document/8547814
- https://riscv-europe.org/summit/2023/media/proceedings/posters/2023-06-07-Karsten-EMRICH-abstract.pdf
- https://ieeexplore.ieee.org/abstract/document/10305465
- https://ieeexplore.ieee.org/abstract/document/9774593/
- https://github.com/Minres/CoreDSL/wiki/CoreDSL-2-programmer's-manual
- https://ieeexplore.ieee.org/abstract/document/9774593
- https://ieeexplore.ieee.org/document/9424273
Prerequisites
- Experience with Low-Level Embedded Systems Programming (Assembly)
- Strong background in C++ and Python programming
- Ideally some knownledge about the RISC-V ISA
- Basic understanding of HW acceleration concepts such as SIMD (single-instruction multiple-data)
- Experience with Git and Debian/Ubuntu based operating systems (or similar)
Contact
philipp,van-kempen@tum.de
Supervisor:
AST Simplification and Optimization for M2-ISA-R Models
Description
M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.
The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.
Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.
Prerequisites
- Interest in learning about symbolic evaluation and simplification
- Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
- Very good knowledge of Python
- Some experience with parser generators, ideally ANTLR4
Contact
karsten.emrich@tum.de
Supervisor:
Automatic Categorization and Filtering of Research Data via Machine Learning Methods
Description
Analog circuit design, to this day, highly depends on expert knowledge. Similarly, efforts in analog design automation include the construction of databases of various sorts, such as analog building blocks, or entire netlists. Much of the necessary knowledge for cunstring such databases is either hidden within the analog designer’s mind, or by extension in published articles. With the recent success in language processing, an opportunity for automatic sighting and analysis of data arises. In this work, experiments with language models will be conducted, with the goal of building a database of articles treating a specific subject in analog design.
Supervisor:
Infinite-order crosstalk analysis for Wavelength-Routed Optical NoCs
Description
(all the details are in the PDF)
Supervisor:
Modelling of novel RISC-V Extensions and Accelerators in CoreDSLPerf for accurate Performance Estimations
ETISS, CoreDSL, CoreDSLPerf, Performance, Modeling
CoreDSLPerf tools allow nearly-cycle accurate simulations of microarchitectural behaviors in virtual prototypes. In addition to the RISC-V standard ISA extensions, further instruction types should be modelled in the future, especially for TinyML applications.
Description
Use CoreDSLPerf to model one or more of the following ISA Extensions + Microarchitecture Implementations:
- RISC-V P(acked) Extension (i.e. on RI5CY core)
- RISC-V V(ector) Extension (i.e. on ARA+Ariane, Vicuna, Spatz)
- RISCV-V B(itmanipulation) Extension (i.e. on RI5CY)
- PULP custom ISA Extensions, such as hardware loops, post-increment load/store, MAC,... (i.e. on RI5CY)
- Special vector extensions (i.e. Andestech D25F, Xuantie C906)
Contact
philipp.van-kempen@tum.de
Supervisor:
Performance Evaluation of a RISC-V CPU
RISC-V, ISS, RTL, ESL, VP, ETISS, Performance, Embedded Systems
Description
This project is proposed and conducted in cooperation with MINRES Technologies.
RISC-V is an open-source instruction set architecture (ISA), which has recently gained a lot of interest in both academia and commercial contexts. One of the key features of the RISC-V architecture is its flexibility, which, for instance, allows chip designers to add custom instructions to support their specific use cases. Further, due to its open-source character, designers are free to implement their own, customized RISC-V microarchitecture.
To fully utilize the flexibility of RISC-V, different design choices should be explored, in order to find the best suited solution. Such a so-called design space exploration (DSE) typically relies on abstract models of the actual hardware, which can be quickly modified to cover different design choices. As high execution speed is frequently of major importance for a processor, accuratly depicting the processor's performance is one of the key requirements for this type of models.
During this project, abstract performance models shall be generated for an existing RISC-V CPU, developted by MINRES Technologies, in order to evaluate its performance. To achieve this, the student will:
- Integrate a tool-chain for performance modelling, developted at TUM, into the simulation environment of MINRES, in order to establish a common workflow.
- Use the established workflow to generate abstract performance models of an existing RISC-V CPU, developted by MINRES.
- Evaluate the accuracy of the generated models, by comparing their performance estimates with the actual performance of the CPU.
Prerequisites
This project requires
- A fundamental understanding of the functionality of processors and basic microarchitectural concepts
- Solid experience in object-oriented programming.
- Experience in programming with C++ and Python3 are a major benefit
Contact
If you are interested in the project or have further questions, please do not hesitate to contact me under conrad.foik@tum.de
Supervisor:
Interdisciplinary Projects
AST Simplification and Optimization for M2-ISA-R Models
Description
M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.
The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.
Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.
Prerequisites
- Interest in learning about symbolic evaluation and simplification
- Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
- Very good knowledge of Python
- Some experience with parser generators, ideally ANTLR4
Contact
karsten.emrich@tum.de
Supervisor:
Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge
Microsystem, MEMS, Innovation, Creativity
This is a dynamic and hands-on internship designed to empower students to harness their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming an innovative entrepreneur in the realm of sensor and microsystem applications. At the end of this contest, you will be credited with the credits for FP/IP/IDP.
Description
Welcome to "Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge," a dynamic and hands-on internship designed to empower students in harnessing their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming innovative entrepreneurs in the realm of sensor and microsystem applications.
Overview:
In this practical internship, students will delve into the world of microsystems, exploring their components, functionalities, and potential applications. The focus will be on fostering creativity and teamwork as students work collaboratively to conceive, design, and prototype innovative solutions using sensors and microsystems.
Key Features:
Creative Exploration: Unlike traditional courses and internships, this one offers the freedom to choose and define your own technical challenge. Students will be encouraged to think outside the box, identify real-world problems, and propose solutions that leverage microsystems to enhance human-technology interactions.
Hands-On Prototyping: The heart of the internship lies in turning ideas into reality. Students will actively engage in the prototyping process, developing functional prototypes of their innovative concepts. Emphasis will be placed on understanding the practical aspects of sensor integration, actuation, and control electronics.
COSIMA Contest Preparation: The internship will align with the COSIMA contest requirements, preparing students to present their prototypes on the competition day. Guidance will be provided on creating impactful presentations that showcase the ingenuity and practicality of their solutions.
Go International: The winners of COSIMA will qualify to take part in the international iCAN competition. Guidance and preparation for the iCAN will be provided.
Entrepreneurial Mindset: Drawing inspiration from successful startups that emerged from COSIMA, the internship will instill an entrepreneurial mindset. Students will learn about the essentials of founding a startup, from business planning to pitching their ideas.
Us in the past:
Das war COSIMA 2023 (cosima-mems.de)
Prerequisites
Intermediate German and English language proficiency is required.
Contact
Supervisor:
Research Internships (Forschungspraxis)
Graph-level Fusing of RISC-V Instructions using CoreDSL
RISCV, CoreDSL, Graph, ISS, ETISS, ISA
The RISC-V instruction set architecture (ISA) is popular due to its extensibility which allows vendors to add custom operations to their application-specific cores. However, proposing and evaluating new instructions usually involves many efforts. There already exist numerous high-level-synthesis (HLS) approaches to automate this procedures by identifying a programs performance bottleneck aka. the critical basic blocks in the Assembly code. Using graph algorithms on the dataflow graph, suitable subgraphs for fusing into a single instruction can be found. To evaluate the newly added instruction we use virtual prototyping tools based on the CoreDSL2 language.
Description
Task Description:
- Literature research (Survey the State of the Art)
- Familarize with used tools (CoreDSL2, ETISS, M2-ISA-R, LLVM)
- Implement instruction fusing methodology based on given RISC-V assembly function (Extract dataflow/dependency graph, detect MIMO subgraphs, generate Instruction in M2-ISA-R metamodel, convert instruction to CoreDSL2 syntax.
- Evaluation of new instructions using ETISS virtual prototype (Generate simulation architecture files, build ETISS, Generate LLVM patches for instruction, build LLVM, build target software, test target software)
- Optional: Develop heuristics to estimate resource overhead for RTL implementation of new instructions.
Related Work/Tools:
- https://llvm.org/pubs/2010-02-IPSJ-CustomInstruction.pdf
- https://www.comp.nus.edu.sg/~tulika/fpt10.pdf
- https://github.com/Minres/CoreDSL/wiki/CoreDSL-2-programmer's-manual
- https://riscv-europe.org/summit/2023/media/proceedings/posters/2023-06-07-Karsten-EMRICH-abstract.pdf
- https://github.com/tum-ei-eda/etiss
Prerequisites
- Experience with RISC-V Assembly
- Deep knowledge about Python programming
- Some experience with CMake for compiling C/C++ projects using GCC/Clang cross-compiler toolchains
- Mathematical understanding of graph partitioning algorithms
Contact
philipp.van-kempen@tum.de
Supervisor:
Porting OpenASIP Custom Operations to CoreDSL Syntax
OpenASIP, EDA, CoreDSL, RISC-V, LLVM
The RISC-V instruction set architecture (ISA) is popular due to its extensibility which allows vendors to add custom operations to their application-specific instruction set processors. Using HW/SW Co-Design approaches and High-level-Synthesis this process can be automated in some degree. There exist custom ASIP generation tools in industry (see Synopsis ASIP Designer and Codasip Studio) as well as open-source alternatives (OpenASIP2.0) from academia.
Description
The goal of this project ist to evaluate the large pool of custom operations supported by the OpenASIP2.0 Co-Design toolchain on our instruction set simulator (ISS) named ETISS using the CoreDSL ecosystem.
Steps:
- Literature Research
- Familiarize with involved tools (OpenASIP, CoreDSL, CoreDSL)
- Collect list of all custom OpenASIP operations
- Develop methodology for translating the custom OpenASIP operations to the CoreDSL syntax
- Generate ETISS architectures using the new instructions
- Evaluate/Test/Benchmark the custom operations
- Optional: Allow ETISS to be used as OpenASIP2.0 target architecture.
Related Literature/Tools:
- https://riscv-europe.org/summit/2023/media/proceedings/posters/2023-06-07-Karsten-EMRICH-abstract.pdf
- https://www.researchgate.net/profile/Ulf-Schlichtmann/publication/322673899_The_extendable_translating_instruction_set_simulator_ETISS_interlinked_with_an_MDA_framework_for_fast_RISC_prototyping/links/5a836128a6fdcc6f3eb28a47/The-extendable-translating-instruction-set-simulator-ETISS-interlinked-with-an-MDA-framework-for-fast-RISC-prototyping.pdf
- https://github.com/tum-ei-eda/etiss
- https://github.com/Minres/CoreDSL/wiki/CoreDSL-2-programmer's-manual
- http://openasip.org/release_2_0.html
- https://zenodo.org/records/6670559
- https://github.com/cpc/openasip
Prerequisites
- Experience with RISC-V ISA (Assembly & Microarchitecture)
- Deep knowledge about Python programming
- Moderate C/C++ experience
Contact
philipp.van-kempen@tum.de
Supervisor:
AST Simplification and Optimization for M2-ISA-R Models
Description
M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.
The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.
Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.
Prerequisites
- Interest in learning about symbolic evaluation and simplification
- Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
- Very good knowledge of Python
- Some experience with parser generators, ideally ANTLR4
Contact
karsten.emrich@tum.de
Supervisor:
Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge
Microsystem, MEMS, Innovation, Creativity
This is a dynamic and hands-on internship designed to empower students to harness their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming an innovative entrepreneur in the realm of sensor and microsystem applications. At the end of this contest, you will be credited with the credits for FP/IP/IDP.
Description
Welcome to "Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge," a dynamic and hands-on internship designed to empower students in harnessing their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming innovative entrepreneurs in the realm of sensor and microsystem applications.
Overview:
In this practical internship, students will delve into the world of microsystems, exploring their components, functionalities, and potential applications. The focus will be on fostering creativity and teamwork as students work collaboratively to conceive, design, and prototype innovative solutions using sensors and microsystems.
Key Features:
Creative Exploration: Unlike traditional courses and internships, this one offers the freedom to choose and define your own technical challenge. Students will be encouraged to think outside the box, identify real-world problems, and propose solutions that leverage microsystems to enhance human-technology interactions.
Hands-On Prototyping: The heart of the internship lies in turning ideas into reality. Students will actively engage in the prototyping process, developing functional prototypes of their innovative concepts. Emphasis will be placed on understanding the practical aspects of sensor integration, actuation, and control electronics.
COSIMA Contest Preparation: The internship will align with the COSIMA contest requirements, preparing students to present their prototypes on the competition day. Guidance will be provided on creating impactful presentations that showcase the ingenuity and practicality of their solutions.
Go International: The winners of COSIMA will qualify to take part in the international iCAN competition. Guidance and preparation for the iCAN will be provided.
Entrepreneurial Mindset: Drawing inspiration from successful startups that emerged from COSIMA, the internship will instill an entrepreneurial mindset. Students will learn about the essentials of founding a startup, from business planning to pitching their ideas.
Us in the past:
Das war COSIMA 2023 (cosima-mems.de)
Prerequisites
Intermediate German and English language proficiency is required.
Contact
Supervisor:
Praktikant (m/w/d) Forschung & Entwicklung - Sensorik Kettenüberwachung
Description
Siehe beigefügten Aushang.
Contact
Claudia.Hahn@iwis.com
Supervisor:
Modelling of novel RISC-V Extensions and Accelerators in CoreDSLPerf for accurate Performance Estimations
ETISS, CoreDSL, CoreDSLPerf, Performance, Modeling
CoreDSLPerf tools allow nearly-cycle accurate simulations of microarchitectural behaviors in virtual prototypes. In addition to the RISC-V standard ISA extensions, further instruction types should be modelled in the future, especially for TinyML applications.
Description
Use CoreDSLPerf to model one or more of the following ISA Extensions + Microarchitecture Implementations:
- RISC-V P(acked) Extension (i.e. on RI5CY core)
- RISC-V V(ector) Extension (i.e. on ARA+Ariane, Vicuna, Spatz)
- RISCV-V B(itmanipulation) Extension (i.e. on RI5CY)
- PULP custom ISA Extensions, such as hardware loops, post-increment load/store, MAC,... (i.e. on RI5CY)
- Special vector extensions (i.e. Andestech D25F, Xuantie C906)
Contact
philipp.van-kempen@tum.de
Supervisor:
Performance Evaluation of a RISC-V CPU
RISC-V, ISS, RTL, ESL, VP, ETISS, Performance, Embedded Systems
Description
This project is proposed and conducted in cooperation with MINRES Technologies.
RISC-V is an open-source instruction set architecture (ISA), which has recently gained a lot of interest in both academia and commercial contexts. One of the key features of the RISC-V architecture is its flexibility, which, for instance, allows chip designers to add custom instructions to support their specific use cases. Further, due to its open-source character, designers are free to implement their own, customized RISC-V microarchitecture.
To fully utilize the flexibility of RISC-V, different design choices should be explored, in order to find the best suited solution. Such a so-called design space exploration (DSE) typically relies on abstract models of the actual hardware, which can be quickly modified to cover different design choices. As high execution speed is frequently of major importance for a processor, accuratly depicting the processor's performance is one of the key requirements for this type of models.
During this project, abstract performance models shall be generated for an existing RISC-V CPU, developted by MINRES Technologies, in order to evaluate its performance. To achieve this, the student will:
- Integrate a tool-chain for performance modelling, developted at TUM, into the simulation environment of MINRES, in order to establish a common workflow.
- Use the established workflow to generate abstract performance models of an existing RISC-V CPU, developted by MINRES.
- Evaluate the accuracy of the generated models, by comparing their performance estimates with the actual performance of the CPU.
Prerequisites
This project requires
- A fundamental understanding of the functionality of processors and basic microarchitectural concepts
- Solid experience in object-oriented programming.
- Experience in programming with C++ and Python3 are a major benefit
Contact
If you are interested in the project or have further questions, please do not hesitate to contact me under conrad.foik@tum.de
Supervisor:
Internships
AST Simplification and Optimization for M2-ISA-R Models
Description
M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.
The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.
Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.
Prerequisites
- Interest in learning about symbolic evaluation and simplification
- Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
- Very good knowledge of Python
- Some experience with parser generators, ideally ANTLR4
Contact
karsten.emrich@tum.de
Supervisor:
Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge
Microsystem, MEMS, Innovation, Creativity
This is a dynamic and hands-on internship designed to empower students to harness their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming an innovative entrepreneur in the realm of sensor and microsystem applications. At the end of this contest, you will be credited with the credits for FP/IP/IDP.
Description
Welcome to "Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge," a dynamic and hands-on internship designed to empower students in harnessing their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming innovative entrepreneurs in the realm of sensor and microsystem applications.
Overview:
In this practical internship, students will delve into the world of microsystems, exploring their components, functionalities, and potential applications. The focus will be on fostering creativity and teamwork as students work collaboratively to conceive, design, and prototype innovative solutions using sensors and microsystems.
Key Features:
Creative Exploration: Unlike traditional courses and internships, this one offers the freedom to choose and define your own technical challenge. Students will be encouraged to think outside the box, identify real-world problems, and propose solutions that leverage microsystems to enhance human-technology interactions.
Hands-On Prototyping: The heart of the internship lies in turning ideas into reality. Students will actively engage in the prototyping process, developing functional prototypes of their innovative concepts. Emphasis will be placed on understanding the practical aspects of sensor integration, actuation, and control electronics.
COSIMA Contest Preparation: The internship will align with the COSIMA contest requirements, preparing students to present their prototypes on the competition day. Guidance will be provided on creating impactful presentations that showcase the ingenuity and practicality of their solutions.
Go International: The winners of COSIMA will qualify to take part in the international iCAN competition. Guidance and preparation for the iCAN will be provided.
Entrepreneurial Mindset: Drawing inspiration from successful startups that emerged from COSIMA, the internship will instill an entrepreneurial mindset. Students will learn about the essentials of founding a startup, from business planning to pitching their ideas.
Us in the past:
Das war COSIMA 2023 (cosima-mems.de)
Prerequisites
Intermediate German and English language proficiency is required.
Contact
Supervisor:
Praktikant (m/w/d) Forschung & Entwicklung - Sensorik Kettenüberwachung
Description
Siehe beigefügten Aushang.
Contact
Claudia.Hahn@iwis.com
Supervisor:
Student Assistant Jobs
Porting OpenASIP Custom Operations to CoreDSL Syntax
OpenASIP, EDA, CoreDSL, RISC-V, LLVM
The RISC-V instruction set architecture (ISA) is popular due to its extensibility which allows vendors to add custom operations to their application-specific instruction set processors. Using HW/SW Co-Design approaches and High-level-Synthesis this process can be automated in some degree. There exist custom ASIP generation tools in industry (see Synopsis ASIP Designer and Codasip Studio) as well as open-source alternatives (OpenASIP2.0) from academia.
Description
The goal of this project ist to evaluate the large pool of custom operations supported by the OpenASIP2.0 Co-Design toolchain on our instruction set simulator (ISS) named ETISS using the CoreDSL ecosystem.
Steps:
- Literature Research
- Familiarize with involved tools (OpenASIP, CoreDSL, CoreDSL)
- Collect list of all custom OpenASIP operations
- Develop methodology for translating the custom OpenASIP operations to the CoreDSL syntax
- Generate ETISS architectures using the new instructions
- Evaluate/Test/Benchmark the custom operations
- Optional: Allow ETISS to be used as OpenASIP2.0 target architecture.
Related Literature/Tools:
- https://riscv-europe.org/summit/2023/media/proceedings/posters/2023-06-07-Karsten-EMRICH-abstract.pdf
- https://www.researchgate.net/profile/Ulf-Schlichtmann/publication/322673899_The_extendable_translating_instruction_set_simulator_ETISS_interlinked_with_an_MDA_framework_for_fast_RISC_prototyping/links/5a836128a6fdcc6f3eb28a47/The-extendable-translating-instruction-set-simulator-ETISS-interlinked-with-an-MDA-framework-for-fast-RISC-prototyping.pdf
- https://github.com/tum-ei-eda/etiss
- https://github.com/Minres/CoreDSL/wiki/CoreDSL-2-programmer's-manual
- http://openasip.org/release_2_0.html
- https://zenodo.org/records/6670559
- https://github.com/cpc/openasip
Prerequisites
- Experience with RISC-V ISA (Assembly & Microarchitecture)
- Deep knowledge about Python programming
- Moderate C/C++ experience
Contact
philipp.van-kempen@tum.de
Supervisor:
AST Simplification and Optimization for M2-ISA-R Models
Description
M2-ISA-R is the code generation toolchain for the instruction set simulator ETISS, both developed by the Chair of Electronic Design Automation at TUM. The core of M2-ISA-R is a meta-model based modeling framework used to represent arbitrary instruction set architectures. Various parsers for architecture description languages and code generators for simulation models use these intermediate models.
The metamodel consists of structural and behavioral components. In this project, the goal is to research, apply and compare various simplification and optimization methods when preprocessing the behavioral syntax tree. A basic expression simplifier is already present, however it is very barebones and lacks required further AST simplification methods.
Depending on experience and individual expectations, the scope of the project can be variable for the chosen project type.
Prerequisites
- Interest in learning about symbolic evaluation and simplification
- Ideally previous experience with static code analysis, natural language processing, compiler engineering etc.
- Very good knowledge of Python
- Some experience with parser generators, ideally ANTLR4
Contact
karsten.emrich@tum.de
Supervisor:
Praktikant (m/w/d) Forschung & Entwicklung - Sensorik Kettenüberwachung
Description
Siehe beigefügten Aushang.
Contact
Claudia.Hahn@iwis.com
Supervisor:
Modelling of novel RISC-V Extensions and Accelerators in CoreDSLPerf for accurate Performance Estimations
ETISS, CoreDSL, CoreDSLPerf, Performance, Modeling
CoreDSLPerf tools allow nearly-cycle accurate simulations of microarchitectural behaviors in virtual prototypes. In addition to the RISC-V standard ISA extensions, further instruction types should be modelled in the future, especially for TinyML applications.
Description
Use CoreDSLPerf to model one or more of the following ISA Extensions + Microarchitecture Implementations:
- RISC-V P(acked) Extension (i.e. on RI5CY core)
- RISC-V V(ector) Extension (i.e. on ARA+Ariane, Vicuna, Spatz)
- RISCV-V B(itmanipulation) Extension (i.e. on RI5CY)
- PULP custom ISA Extensions, such as hardware loops, post-increment load/store, MAC,... (i.e. on RI5CY)
- Special vector extensions (i.e. Andestech D25F, Xuantie C906)
Contact
philipp.van-kempen@tum.de