Synthesis of Digital Systems
| Lecturer (assistant) | |
|---|---|
| Number | 0000003198 |
| Type | lecture with integrated exercises |
| Duration | 3 SWS |
| Term | Summer semester 2026 |
| Language of instruction | English |
| Position within curricula | See TUMonline |
Admission information
See TUMonline
Note: Note: Maximal number of participants is 50. Registration for lecture and lab is done via the Reihung Masterpraktika. the lecture and lab have to be done together. Participation at the scheduled lab session is mandatory. Students from the waiting list can participate if registered students do not show up.
Note: Note: Maximal number of participants is 50. Registration for lecture and lab is done via the Reihung Masterpraktika. the lecture and lab have to be done together. Participation at the scheduled lab session is mandatory. Students from the waiting list can participate if registered students do not show up.
Description
Summer semester: Course will be in German language in presence, exam will be in presence in English and German. Laboratory virtual/online.
The following topics are covered during the lecture and exercises:
- Introduction to the synthesis steps and the design flow of digital systems
- Static code analysis and code optimisation
- High-level hardware synthesis including data path design, ASAP-, ALAP- and List-Scheduling, binding with Left-Edge algorithm, control path design
- Software compilation and execution including compilation steps, ARM assembly code generation, instruction set architectures, register allocation, RISC pipeline, data and control hazards, estimation of execution times
- Introduction to HW/SW interfaces, system models and load balancing algorithms
The following applications are covered in the practical lab sessions:
- Hands-on training on an industrial high level synthesis (HLS) tool
- Implementation of a HW peripheral using HLS
- Implementation of the HW/SW interface
- Synthesis and execution on an FPGA board
The following topics are covered during the lecture and exercises:
- Introduction to the synthesis steps and the design flow of digital systems
- Static code analysis and code optimisation
- High-level hardware synthesis including data path design, ASAP-, ALAP- and List-Scheduling, binding with Left-Edge algorithm, control path design
- Software compilation and execution including compilation steps, ARM assembly code generation, instruction set architectures, register allocation, RISC pipeline, data and control hazards, estimation of execution times
- Introduction to HW/SW interfaces, system models and load balancing algorithms
The following applications are covered in the practical lab sessions:
- Hands-on training on an industrial high level synthesis (HLS) tool
- Implementation of a HW peripheral using HLS
- Implementation of the HW/SW interface
- Synthesis and execution on an FPGA board
Prerequisites
The participation in a VHDL lab before this lecture is encouraged. Basic knowledge of C programming and assembly code is desired.
Teaching and learning methods
The lecture is divided into lecture, exercise and lab sessions (50%), as well as self-study time (50%).
During lecture and exercises, subjects are taught with a mix of methods. This includes frontal methods such as presentations on specific topics and assignments derived on the black board as well as various activating methods ranging from individual assignments and team assignments to team discussions.
The hands-on lab sessions are usually worked on in small teams. The lab sessions are strongly aligned with the lecture's topics to ensure that the theory learned during lecture can be applied to practical design problems. For this, modern EDA tools are used.
Additionally, individual and independent work is done on practical assignments in the self-study time. An e-learning platform is used to provide the learning materials to the students.
During lecture and exercises, subjects are taught with a mix of methods. This includes frontal methods such as presentations on specific topics and assignments derived on the black board as well as various activating methods ranging from individual assignments and team assignments to team discussions.
The hands-on lab sessions are usually worked on in small teams. The lab sessions are strongly aligned with the lecture's topics to ensure that the theory learned during lecture can be applied to practical design problems. For this, modern EDA tools are used.
Additionally, individual and independent work is done on practical assignments in the self-study time. An e-learning platform is used to provide the learning materials to the students.
Links
Bachelorbereich: BSc-EI, BSES, BSEDE
| SS | Diskrete Mathematik für Ingenieure (BSEI, EI00460) (Schlichtmann) | |
| WS | Discrete Mathematics for Engineers (BSEDE) (Schlichtmann) | |
| WS | Grundlagen der Elektrotechnik I (BSES, EI10014) (Schlichtmann) | |
| WS | SS | Entwurf digitaler Systeme mit VHDL u. System C (BSEI, EI0690) (Ecker) |
| SS | Entwurfsverfahren für integrierte Schaltungen (BSES, EI43811) (Schlichtmann) | |
| SS | Schaltungssimulation (BSEI, EI06691) (Schlichtmann/ Leibl) |
Masterbereich: MSc-EI, MSCE, ICD
| SS | Advanced Topics in Communication Electronics (MSCE, EI79002) | ||
| SS | Electronic Design Automation (MSMCD, MSCE, MSEI, EI70610) (Schlichtmann, Tseng) | ||
| WS | Design Methodology and Automation (ICD) (Schlichtmann) | ||
| WS | Embedded System Design for Machine Learning (MSCE, MSEI, EI71040) (Ecker) | ||
| SS | Simulation and Optimization of Analog Circuits (ICD) (Gräb) | ||
| SS | Mixed Integer Programming and Graph Algorithms in Engineering Problems (MSMCD, MSCE, MSEI, EI71059) (Tseng) | ||
| WS | SS | Numerische Methoden der Elektrotechnik (MSEI, EI70440) (Schlichtmann/ Truppel) | |
WS WS | SS | Seminar VLSI-Entwurfsverfahren (MSEI, EI7750) (Schlichtmann) Seminar on Topics in Electronic Design Automation (MSMCD, MSCE, EI77502) (Schlichtmann) | |
| WS | SS | Synthesis of Digital Systems (MSCE, MSEI, EI70640) (Geier) | |
| WS | Testing Digital Circuits (MSMCD, MSCE, MSEI, EI50141) (Otterstedt) | ||
| WS | SS | VHDL System Design Laboratory (MSCE, MSEI, EI7403) (Schlichtmann) | |
| WS | SS | HDL Chip Design Laboratory (MSMCD, CIT431016) (Schlichtmann) |
BSES: Bachelor of Science Engineering Science (TUM-ED)
BSEDE: Bachelor of Science in Electronics and Data Engineering (TUM-Asia)
ICD: Master of Science in Integrated Circuit Design (TUM-Asia)
MSMCD: Master of Science in Microelectronics and Chip Design (TUM)
MSCE: Master of Science in Communications Engineering (TUM)
MSEI: Master of Science in Elektrotechnik und Informationstechnik
BSEI: Bachelor of Science in Elektrotechnik und Informationstechnik