Digital System Design with VHDL and System C

Lecturer (assistant)
Number0000003406
Type
Duration4 SWS
TermWintersemester 2022/23
Language of instructionGerman
Position within curriculaSee TUMonline

Admission information

See TUMonline
Note: Registration on TUMOnline before the first lecture.

Objectives

The students will learn the abstraction, modeling and design techniques. Furthermore, the students will be familiar with an industrial design system and the modeling language VHDL (WS) and System C (SS).

Description

The course is very work intensive, since three models need to be built. There is no time to attend other seminars, work on a thesis or do an internship in the period of the course. The return of assignments must be via Moodle according to schedule. Groups with up to 4 students may be formed to build the model. The contribution of each student to the model must be documented in the model. Delivery deadlines are: Memory Model tbd CPU Model tbd RTL Model tbd The simulation of the models is essential, the tool Vivado from Xilinx can (and must) be downloaded for that purpose. Models will be reviewed and contribute overall 50% to the final grade. The final oral examination will be done in groups of two students. Schedules will be arranged case by case. The duration of the examination is 30-45 Minutes. The content of the lecture covers the Hardware description languages VHDL and SystemC, design methodology with VHDL and SystemC, VHDL/SystemC modeling, VHDL/SystemC simulation and VHDL register-transfer synthesis. There will be computer lab exercises in VHDL/SystemC modeling, automatic synthesis and selected synthesis methods.

Prerequisites

Basic knowledge in digital design; one programming language (at best C or C++) is absolutely necessary.

Teaching and learning methods

As teaching method learning using examples will be used. According to one example (a MIPS2 subsystem) the requirements are motivated, presented and then generalized. The learning content will be deepened by team work and incorporation of industrial working styles.

Examination

Examination with following parts: - Written examination at the end of the course (60 min., no notes allowed) (50%) - Graded homework/projects (4 parts: memory model, functional CPU model, behavioral CPU model, RTL CPU model) (50%)

Recommended literature

Following materials are recommended: * Computer Organization And Design The Hardware/Software Interface; David A. Patterson, John L. Hennessy, Elsevier * John L. Hennessy, David A. Patterson: Computer Architecture - A Quantitative Approach, Elsevier / Morgan Kaufmanns Publishers. * Dominic Sweetman: See MIPS Run Linux, Elsevier / Morgan Kaufmanns Publishers. * Peter Ashenden: The Designer’s Guide to VHDL, Morgan Kaufmann Series in Systems on Silicon) * Thinking in C++ 2nd Edition by Bruce Eckel * SystemC: From the Ground Up (the Kluwer International Series in Engineering & Computer Science) (Hardcover) * Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems. Internet Resources: * http://en.wikipedia.org/wiki/MIPS_architecture * http://www.mips.com/products/processors/ * http://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf

Links


All courses

Bachelorbereich: BSc-EI, MSE, BSEDE

 

WS

SS

Diskrete Mathematik für Ingenieure (BSEI, EI00460)

Discrete Mathematics for Engineers (BSEDE ) (Schlichtmann) (Januar)

 

 

WS

SS

Entwurf digitaler Systeme mit VHDL u. System C (BSEI, EI0690) (Ecker)

 

 

SS

Entwurfsverfahren für integrierte Schaltungen (MSE, EI43811) (Schlichtmann)

 

WS

 

Methoden der Unternehmensführung (BSEI, EI0481) (Weigel)

 

WS

 

Praktikum System- und Schaltungstechnik (BSEI, EI0664) (Schlichtmann et al.)

 

 

SS

Schaltungssimulation (BSEI, EI06691) (Gräb/Schlichtmann)

 

 

Masterbereich: MSc-EI, MSCE, ICD

 

SS

Advanced Topics in Communication Electronics (MSCE, MSEI, EI79002)

 

WS

 

Electronic Design Automation (MSCE, MSEI, EI70610) (B. Li, Tseng)

 

WS

 

Design Methodology and Automation (ICD) (Schlichtmann) (Nov)

 

WS

SS

Machine Learning: Methods and Tools (MSCE, MSEI, EI71040) (Ecker)

 

WS

SS

SS

Mathematical Methods of Circuit Design (MSCE, MSEI, EI74042) (Gräb)

Simulation and Optimization of Analog Circuits (ICD) (Gräb) (Mai)

 

 

WS

 

Mixed Integer Programming and Graph Algorithms in Engineering Problems (MSCE, MSEI, EI71059) (Tseng)

 

WS

SS

Numerische Methoden der Elektrotechnik (MSEI, EI70440) (Schlichtmann oder Gräb)

 

WS

WS

SS

Seminar VLSI-Entwurfsverfahren (MSEI, EI7750) (Schlichtmann/Müller-Gritschneder)

Seminar on Topics in Electronic Design Automation (MSCE, EI77502) (Schlichtmann/Müller-Gritschneder)

 

 

WS

SS

Synthesis of Digital Systems (MSCE, MSEI, EI70640) (Müller-Gritschneder)

 

WS

 

Testing Digital Circuits (MSCE, MSEI, EI50141) (Otterstedt)

 

WS

 

Timing of Digital Circuits (MSCE, MSEI, EI70550) (B. Li, Zhang)

 

WS

SS

VHDL System Design Laboratory (MSCE, MSEI, EI7403) (Schlichtmann)

 

MSE: Munich School of Engineering (TUM)

BSEDE: Bachelor of Science in Electronics and Data Engineering (TUM-Asia)

ICD: Master of Science in Integrated Circuit Design (TUM-Asia)

MSCE: Master of Science in Communications Engineering (TUM)

MSEI: Master of Science in Elektrotechnik und Informationstechnik

BSEI: Bachelor of Science in Elektrotechnik und Informationstechnik

 

Aktuelle Infos zur Lehre/Current information on teaching: https://www.tum.de/die-tum/aktuelles/coronavirus/studium/, www.ei.tum.de