Skip to content
Technical University of Munich
Back to list Next Previous

HDL Chip Design Laboratory

Lecturer (assistant)
Chuangtao Chen
Yushen Zhang
Ulf Schlichtmann
Number 0000002691
Type practical training
Duration 4 SWS
Term Wintersemester 2025/26
Language of instruction English
Position within curricula See TUMonline

Admission information

See TUMonline
Note: Attendance of the FIRST LECTURE is MANDATORY for all students, and any student who misses the first lecture will be removed from the course. Please note that only students who have received the status "Confirmed place/Fixplatz" have a spot in this course. All students with "Requirements met/Voraussetzungen erfüllt" are on the waiting list. If you are on the waiting list and still wish to attend the course, we strongly recommend that you join the first lecture, as you still have a chance to get into the course. Please note that any student who does not show up for the first lecture will be removed and will be replaced by students on the waiting list who attend the first lecture.

Objectives

By the end of this module, students will be able to apply the fundamentals of the Verilog hardware description language to implement and verify digital systems on an FPGA. They will be capable of creating individual digital communication modules—such as UART interfaces, source/channel encoders, and modulators—integrating them into a complete system, and validating functionality through a standard FPGA design flow, including simulation and hardware implementation.

Description

This course introduces the basics of hardware description language (Verilog). The students are required to design and implement a simplified digital baseband processor on FPGA. The practical part consists of the following contents:
Build an end-to-end communication chain including a UART interface for data transfer, Huffman source encoding, convolutional channel encoding, and 16-QAM digital modulation.
Apply hardware description languages to design each module, integrate them into a complete system, and verify the design through simulation and FPGA implementation.
The course requires basic knowledge of digital circuits design, such as combinational logic, finite state machines.

Prerequisites

Fundamentals of digital circuits
Fundamentals of programming

Teaching and learning methods

Teaching Method:
The course is delivered through a blend of direct instruction and supported, independent lab work.

Lectures: The course begins with instructor-led lectures to introduce core concepts.
Laboratory Work: For the practical part of the course, students are provided with an FPGA board, a detailed task manual, and test codes.
Flexible Support: Students have the flexibility to work in a dedicated lab room or on their own PCs. Tutors are available in the lab during scheduled hours each week to provide direct instruction, answer questions, and offer support.

Learning Method:
The course follows a structured, two-phase approach to build both theoretical knowledge and practical skills.

1. Foundational Learning: Students begin by acquiring a solid understanding of Verilog HDL through several theoretical lectures. This knowledge is reinforced with lecture slides and an interactive web platform for hands-on practice.
2. Applied Learning: Following the lectures, students transition to a semester-long laboratory project. They apply their knowledge by working through a series of guided tasks of increasing complexity, as outlined in the provided task manual. This project-based method ensures students learn by doing, culminating in the implementation of a complete digital system.

Examination

Assessment of the module's learning outcomes is based on the evaluation of student-submitted code for the practical laboratory tasks. Additionally, students have the opportunity to participate in a final exam.

Programming Tasks:
Through the programming tasks, students demonstrate their ability to design and develop an digital system on FPGA. For this purpose, students write HDL code for a given system, perform simulations of the system, test their system on an FPGA, debug their code, and document the components they have developed.

Final Exam (graded written exam, 60 minutes):

In the final exam, students will demonstrate their comprehensive understanding of designing digital systems on FPGAs. The assessment is composed of two parts. The first part will test theoretical knowledge, covering fundamental concepts of Verilog HDL, FPGA design flows, and digital logic. The second part will focus on practical application, with questions drawn from the laboratory assignments to evaluate students' ability to analyze their own code.

Recommended literature

The following literature is recommended:
* "IEEE Standard for Verilog Hardware Description Language," in IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001) , vol., no., pp.1-590, 7 April 2006, doi: 10.1109/IEEESTD.2006.99495.
* Palnitkar, Samir, Verilog HDL: A Guide to Digital Design and Synthesis, Upper Saddle River, NJ, 2003, ISBN 9780130449115.
* More literature listed in laboratory notes

Links

Back to list Next Previous

All courses

Bachelorbereich: BSc-EI, BSES, BSEDE

 SSDiskrete Mathematik für Ingenieure (BSEI, EI00460) (Schlichtmann)
WS Discrete Mathematics for Engineers (BSEDE) (Schlichtmann) 
WS Grundlagen der Elektrotechnik I (BSES, EI10014) (Schlichtmann)
WSSSEntwurf digitaler Systeme mit VHDL u. System C (BSEI, EI0690) (Ecker)
 SSEntwurfsverfahren für integrierte Schaltungen (BSES, EI43811) (Schlichtmann)
 SSSchaltungssimulation (BSEI, EI06691) (Schlichtmann/ Leibl)

 

Masterbereich: MSc-EI, MSCE, ICD

 SSAdvanced Topics in Communication Electronics (MSCE, EI79002) 
 SSElectronic Design Automation (MSMCD, MSCE, MSEI, EI70610) (Schlichtmann, Tseng) 
WS Design Methodology and Automation (ICD) (Schlichtmann) 
WS Embedded System Design for Machine Learning (MSCE, MSEI, EI71040) (Ecker) 
 SSSimulation and Optimization of Analog Circuits (ICD) (Gräb) 
 SSMixed Integer Programming and Graph Algorithms in Engineering Problems (MSMCD, MSCE, MSEI, EI71059) (Tseng) 
WSSSNumerische Methoden der Elektrotechnik (MSEI, EI70440) (Schlichtmann/ Truppel) 

WS

WS

SS

Seminar VLSI-Entwurfsverfahren (MSEI, EI7750) (Schlichtmann)

Seminar on Topics in Electronic Design Automation (MSMCD, MSCE, EI77502) (Schlichtmann)

 
WSSSSynthesis of Digital Systems (MSCE, MSEI, EI70640) (Geier) 
WS Testing Digital Circuits (MSMCD, MSCE, MSEI, EI50141) (Otterstedt) 
WSSSVHDL System Design Laboratory (MSCE, MSEI, EI7403) (Schlichtmann) 
WSSSHDL Chip Design Laboratory (MSMCD, CIT431016) (Schlichtmann) 

BSES: Bachelor of Science Engineering Science (TUM-ED)

BSEDE: Bachelor of Science in Electronics and Data Engineering (TUM-Asia)

ICD: Master of Science in Integrated Circuit Design (TUM-Asia)

MSMCD: Master of Science in Microelectronics and Chip Design (TUM)

MSCE: Master of Science in Communications Engineering (TUM)

MSEI: Master of Science in Elektrotechnik und Informationstechnik

BSEI: Bachelor of Science in Elektrotechnik und Informationstechnik

To top