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Technical University of Munich
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Digital System Design with VHDL

Lecturer (assistant)
Wolfgang Ecker
Number 0000005077
Type lecture with integrated exercises
Duration 4 SWS
Term Sommersemester 2025
Language of instruction English
Position within curricula See TUMonline

Admission information

See TUMonline

Objectives

The students will learn the abstraction, modeling and design techniques. Furthermore, the students will be familiar with an industrial design system and the modeling language VHDL (WS) and SystemC (SS).

Description

The return of assignments must be via Moodle according to schedule. Groups with up to 4 students may be formed to build the model. The contribution of each student to the model must be documented in the model.
Delivery deadlines to be announced

The simulation of the models is essential, the tool Vivado from Xilinx can (and must) be downloaded for that purpose.

Models will be reviewed and contribute overall 50% to the final grade.

The content of the lecture covers the Hardware description languages VHDL and SystemC, design methodology with VHDL and SystemC, VHDL/SystemC modeling, VHDL/SystemC simulation and VHDL register-transfer synthesis. There will be computer lab exercises in VHDL/SystemC modeling, automatic synthesis and selected synthesis methods.


Hardware description language VHDL and SystemC, design methodology with VHDL and SystemC, VHDL/SystemC modeling, VHDL/SystemC simulation and VHDL/SystemC synthesis, methods of logic synthesis, register-transfer synthesis and high-level synthesis; computer lab exercises in VHDL/SystemC modeling, automatic synthesis and selected synthesis methods.

Prerequisites

Basis knowledge of digital design and programming language (C or C++) is absolutely necessary.

Teaching and learning methods

Exemplary learning is used. With help of an MIPS2 subsystem the requirements will be motivated, represented and generalized. The understanding will be deepened by team work under industrial techniques.

Following media will be used:
- Presentations as handouts
- Case studies
- Template solutions

Examination

Module examination with the following components:
- Final exam, 60 min (50%)
- Graded homework and projects (Several mdoules and architecture elements of a RISC-V processor) (50%)

In the final exam, it is demonstrated across all sub-steps of the design of an electronic system that the student is able to analyze a design problem and find appropriate solution steps in a given time. During the semester, the student demonstrates that he/she is able to work independently on design tasks as a project using four major system components.

Recommended literature

Following literature is recommended:
* Computer Organization And Design The Hardware/Software Interface; David A. Patterson, John L. Hennessy, Elsevier
* John L. Hennessy, David A. Patterson: Computer Architecture - A Quantitative Approach, Elsevier / Morgan Kaufmanns Publishers.
* Dominic Sweetman: See MIPS Run Linux, Elsevier / Morgan Kaufmanns Publishers.
* Peter Ashenden: The Designer’s Guide to VHDL, Morgan Kaufmann Series in Systems on Silicon)
* Thinking in C++ 2nd Edition by Bruce Eckel
* SystemC: From the Ground Up (the Kluwer International Series in Engineering & Computer Science) (Hardcover)
* Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems.

Internet Resources:
http://en.wikipedia.org/wiki/MIPS_architecture
http://www.mips.com/products/processors/
http://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf

Links

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All courses

Bachelorbereich: BSc-EI, BSES, BSEDE

WSSSDiskrete Mathematik für Ingenieure (BSEI, EI00460) Discrete Mathematics for Engineers (BSEDE ) (Schlichtmann) (Januar)
WSSSEntwurf digitaler Systeme mit VHDL u. System C (BSEI, EI0690) (Ecker)
 SSEntwurfsverfahren für integrierte Schaltungen (BSES, EI43811) (Schlichtmann)
 SSSchaltungssimulation (BSEI, EI06691) (Gräb/Schlichtmann)

 

Masterbereich: MSc-EI, MSCE, ICD

 SSAdvanced Topics in Communication Electronics (MSCE, MSEI, EI79002) 
 SSElectronic Design Automation (MSCE, MSEI, EI70610) (Schlichtmann, Tseng) 
WS Design Methodology and Automation (ICD) (Schlichtmann) (Nov) 
WSSSEmbedded System Design for Machine Learning (MSCE, MSEI, EI71040) (Ecker) 
 SSSimulation and Optimization of Analog Circuits (ICD) (Gräb) (Mai) 
 SSMixed Integer Programming and Graph Algorithms in Engineering Problems (MSCE, MSEI, EI71059) (Tseng) 
WSSSNumerische Methoden der Elektrotechnik (MSEI, EI70440) (Schlichtmann oder Truppel) 

WS

WS

SS

Seminar VLSI-Entwurfsverfahren (MSEI, EI7750) (Schlichtmann)

Seminar on Topics in Electronic Design Automation (MSCE, EI77502) (Schlichtmann)

 
WSSSSynthesis of Digital Systems (MSCE, MSEI, EI70640) (Geier) 
WS Testing Digital Circuits (MSCE, MSEI, EI50141) (Otterstedt) 
WSSSVHDL System Design Laboratory (MSCE, MSEI, EI7403) (Schlichtmann) 

BSES: Bachelor of Science Engineering Science (TUM-ED)

BSEDE: Bachelor of Science in Electronics and Data Engineering (TUM-Asia)

ICD: Master of Science in Integrated Circuit Design (TUM-Asia)

MSCE: Master of Science in Communications Engineering (TUM)

MSEI: Master of Science in Elektrotechnik und Informationstechnik

BSEI: Bachelor of Science in Elektrotechnik und Informationstechnik

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