Supervisor: Prof. Dr.-Ing. Carsten Trinitis

Contact: Kun Qin, kun.qin(at)tum(dot)de

RISC-V's openness, flexibility, and innovation drive the study and research of the RISC-V Instruction Set Architecture (ISA) within simulators such as gem5 or QEMU. Being an open-source ISA, RISC-V allows researchers, developers, and students to explore and innovate in processor design without the constraints of proprietary ISAs. Simulators facilitate this exploration by providing a platform for modeling, simulating, and evaluating architectural changes and their impacts on performance and power consumption without physical hardware. This setup is invaluable for educational purposes, enabling hands-on learning experiences in computer architecture and hardware-software co-design, where processor and software systems are optimized together. Furthermore, simulators support cross-platform development, virtualization, and the detailed analysis needed for performance optimization, contributing to the growth of the RISC-V ecosystem. The combination of RISC-V's openness and the comprehensive simulation tools accelerates the development, testing, and deployment of RISC-V-based systems across various applications, from embedded systems to high-performance computing, making it a fertile ground for innovation and education in computer systems design.

The contents of this project/thesis are as follows:

• Literature research on:
  •     RISC-V ISA and the ecosystem (i.e., build tools and existing versions),
  •     At least one simulation framework and the compatibility for RISC-V,
  •     Related works and the-state-of-art method.
• Develop a simple baseline model, i.e., an implementation of a system-level ISA simulation without any support of interrupts or peripherals.
• Implementation of an interface that enables customized instructions.
• Complete testing of the full system simulation of the standard ISA.
• Evaluation of the simulation firmware:
  •     Find suitable benchmarks with approporiate criteria of selection,
  •     Illustrate the performance of the simulation tool (cycles per instruction, CPU run-time, coverage of the ISA, etc).
• Documantation of all your findings and results.
• Optional:
  • Develop an extension of the baseline model that enables interrupts and basic periphery (UART, I2C),
  • Comparison of the simulator to a real RISC-V core and try to calibrate the simulation,
  • Customized instructions.

Prerequisites:

• Fundamentals about computer architecture and RISC-V
• C++/Python

This project aims to establish a high-performance computing cluster using single-board computers (SBCs) powered by RISC-V processors and running the Linux operating system.

Hardware: Beagle-V Ahead SBC powered by RISC-V 

Goals:

• Hardware Setup:  Assemble the cluster by installing Linux on multiple RISC-V SBCs.
• Network Configuration: Establish network connectivity between the SBCs for communication and resource sharing.
• Cluster Management: Configure software tools for cluster management, allowing users to submit and run jobs across the entire cluster.
• User Management: Create a system for adding, removing, and managing user accounts on the cluster for secure access and job control.

Tasks:

• OS Installation: Install the chosen Linux distribution on each SBC, following vendor-specific instructions or generic RISC-V installation guides.
• Network Configuration: Configure network interfaces on each SBC for communication within the cluster. This may involve static IP assignment or using a DHCP server.
• Cluster Management Setup: Install and configure the chosen cluster management software on each node. This enables coordinated execution of tasks across the cluster.
• User Management: Establish a user management system for the cluster. This could involve creating local accounts on each node or using a centralized authentication system.
• Testing and Validation: Test the functionality of the cluster by running simple parallel tasks and verifying communication between nodes.

Deliverables:

•  A functional RISC-V cluster running Linux.
• A documented process for adding new nodes to the cluster.
• A user management system for accessing and running jobs on the cluster.

Benefits:

• Gain hands-on experience with RISC-V architecture.
• Learn about cluster computing principles and software.
• Create a powerful and scalable computing platform for various projects.

Designing a platform for test automation of Verilog coding in hardware design education is fundamentally motivated by the desire to enhance the practical learning experience and bridge the gap between theoretical knowledge and its real-world application. This platform provides immediate feedback, crucial for students to quickly identify and rectify errors in their designs, thereby deepening their understanding of digital logic and circuit design. It facilitates hands-on experience with hardware description languages, essential for careers in hardware design and FPGA development, and streamlines the verification process, enabling rapid prototyping and more efficient project iterations. Such a platform encourages experimentation within a safe, controlled environment, fostering innovation and creative problem-solving skills that are highly valued in the industry. Moreover, by introducing students to automated testing practices common in the professional sphere, the platform prepares them for the workforce, ensuring they possess skills in demand. Additionally, it supports remote and collaborative learning, making hardware design education more accessible and adaptable to various learning modalities. Overall, this initiative aims to standardize evaluation, improve the quality of education, and enable educators to manage larger classes effectively, ultimately preparing students for the complexities of modern hardware development.

Current Phase: GitLab + Artemis (Customized Docker)

• Repository Setup:
  •   Create a repository for each student or team to upload their Verilog code. GitHub and GitLab provide excellent version control, useful for tracking progress and revisions.
• Continuous Integration (CI) Tools:
  • Utilize the CI/CD (Continuous Integration/Continuous Deployment) pipelines available in GitHub (Actions) and GitLab (CI/CD) to automate the testing of Verilog code. Configure the pipeline to compile the Verilog code, run simulations, and check for correctness against predefined test cases.
• Automated Feedback:
  • Set up the CI pipeline to generate feedback reports. This can include compilation errors, simulation logs, and test case results, which are then automatically shared with the student or team through the platform.
• Integration with External Tools:
  • Integrate external simulation tools and compilers (e.g., Icarus Verilog, Verilator) into the CI environment. This might require custom Docker containers or scripts within the CI pipeline.
• Documentation and Examples:
  •  Provide comprehensive guides, examples, and resources within the platform to help students learn how to use the tools, write testbenches, and interpret feedback.

Next Phase: Web APP (localhost)

• Web Framework Selection:
  • Choose a web framework as the foundation of your WebApp. Consider the ease of development, community support, and scalability.
• User Management:
  • Implement user authentication and authorization to manage access for students, instructors, and administrators. This allows for personalized dashboards and project management.
• Verilog Compiler and Simulator Integration:
  • Integrate Verilog compilation and simulation tools directly into the WebApp. This could be done through backend services that process the uploaded code, simulate it, and return results.
• (Optional) Interactive IDE:
  • Incorporate an online Integrated Development Environment (IDE) that supports Verilog syntax highlighting.
• Automated Testing and Feedback System:
  • Develop a backend system that automatically tests submitted Verilog code against predefined testbenches, providing instant feedback on the correctness and performance of the code.
• Resource and Learning Material:
  • Include a section for learning materials, tutorials, and examples that guide students through Verilog coding, testbench creation, and interpretation of simulation results.
• Collaboration Features:
  • Add features to enable peer review, code sharing among students, and instructor feedback, fostering a collaborative learning environment.