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Technical University of Munich

Kun Qin, M.Sc

Doctoral Candidate & Research Associate

IH02 Chair of Computer Architecture and Operating Systems, CAOS (Prof. Trinitis)
I10 Chair of Computer Architecture and Parallel Systems, CAPS (Prof. Schulz)
Department of Computer Engineering
School of Computation, Information and Technology
Technical University of Munich

Postal Address: 
Bildungscampus 2, 74076 Heilbronn
Office: D.3.20

Email: kun.qin'at' tum.de

Research Interests

  • Hardware/software codesign
  • RISC-V and open-source architectures
  • FPGA/ASIC design and implementations
  • Quantum computing and quantum-based systems

Teaching

  • Introduction to HDL and Tools: WS23/24, SS24, WS24/25, WS25/26
  • TA: Introduction to Computer Architecture and Technology: WS23/24, WS24/25

Academic Services

  • Web chair of ACM International Conference on Computing Frontiers (CF'24, CF'25)
  • Publicity chair of ACM International Conference on Computing Frontiers (CF'26)

Publications

  • Xiaorang Guo, Kun Qin, Yanbin Chen, Carsten Trinitis, and Martin Schulz. Vectorizing Quantum Control: A RISC-V Vector Extension Architecture for Scalable Qubit Systems.  In IEEE International Conference on Quantum Computing and Engineering (QCE26), Toronto, Ontario, Canada. preprint: https://arxiv.org/abs/2607.07372
  • Kun Qin, Aswathy N. Sankaranarayanan, Taiki Okano, Martin Schulz, and Carsten Trinitis. 2026. Towards a RISC-V-based SmartNIC Architecture on FPGA. In Proceedings of the 23rd ACM International Conference on Computing Frontiers (CF '26), May 19--21, 2026, Catania, Italy. ACM, New York, NY, USA. https://doi.org/10.1145/3801487.3805615
  • Nima Baradaran Hassanzadeh, Jakob Schäffeler, Kun Qin, Carsten Trinitis, and Martin Schulz. LIBERO: A Flexible, Lightweight GDB-based Visualization Tool for RISC-V Vector Extensions. In Proceedings of the 39th GI/ITG International Conference on Architecture of Computing Systems, March 24-26, 2026, Mainz, Germany.
  • Kun Qin, Xiaorang Guo, Martin Schulz, and Carsten Trinitis. 2025. FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors. In 22nd ACM International Conference on Computing Frontiers (CF ’25), May 28–30, 2025, Cagliari, Italy. ACM, New York, NY, USA, 9 pages. https://dl.acm.org/doi/10.1145/3719276.3725174
  • Xiaorang Guo, Kun Qin, and Martin Schulz, HiSEP-Q: A Highly Scalable and Efficient Quantum Control Processor for Superconducting Qubits, 2023 IEEE 41st International Conference on Computer Design (ICCD), Washington, DC, USA, 2023, pp. 86-93, DOI: 10.1109/ICCD58817.2023.00023
  • Kun Qin and Carsten Trinitis. “Best Poster Award” at SERESSA 2023, December 4-7, Turin, Italy, 2023. A compact high-precision FPGA-based Time-to-digital Converter. News
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