Design Space Exploration using Software Simulators

Lecturer: Aswathy Nedumpalli Sankaranarayanan

ECTS: 5

Type: Lecture, 2V+1Ü

Language: English

 

Description

This course introduces Design Space Exploration (DSE) as a structured methodology for analyzing and optimizing architectural design decisions in modern processors and systems-on-chip. Students explore cache hierarchies, multicore systems, interconnects, and memory subsystems through simulation-based analysis of performance trade-offs. The course extends to physical-aware DSE by incorporating power, area, and frequency constraints, and concludes by connecting architectural exploration with RTL simulation and physical design flows.

Contents

1. Introduction to Design Space Exploration (DSE)
2. Introduction to simulators: Functional (QEMU), Cycle-accurate (Gem5), Specialized simulators
3. Benchmarking and workloads
4. Cache hierarchy exploration using Gem5
5. Multi-core systems using GVSoC
6. NoC Interconnects: Gem5-garnet
7. Memory subsystem: DRAMSim, Ramulator
8. Physical-aware DSE: CACTI, McPAT, Hotspot
9. RTL simulation basics: Verilator

Teaching materials

Teaching materials are available on Moodle. You will be automatically activated for the Moodle course when you register for TUMOnline.